Design Techniques For Nanoscale 10-bit High-speed SAR A/D Converters

As the society have stepped into "smart era”, smart machines and sensing device that around us have a large demand of high performance ADC(analog-to-digital converter).SAR ADC(successive approximation register ADC) is one of common structure ADC.As Moore's law predicts that chips' integration is higher and higher, power consumption is an increasing serious problem.SAR ADC have a natural advantage that is low power consumption, this advantage makes it very outstanding, loved by a lot of people. Usually, SAR ADC is generally applied in low speed occasion. But with the progress of CMOS technology and the application of asynchronous sequential, the speed of SAR ADC had an obvious rise. Under the same accuracy, it can be even comparable to the Flash ADC, achieve a GHz level. At the same time, SAR ADC has the congenital superiority in power consumption and chip size, so the SAR ADC is the current hot research direction. Based on this background, this paper discusses the SAR ADC performance under the nanometer technology, designed a 10 bits high-speed SAR ADC chip under 65 nm process.SAR ADC mainly includes three parts: capacitor array, comparator and digital control logic. Learn experience of predecessors, combined with the design details, this article made a theoretical support for the two levels weight capacitor array, analyzed the advantages and disadvantages of it, and calculate the unit capacity; Discussed the comparator principle, considered its delay time, adopt a dynamic comparator with a preamplifier. Improved the first bit of the capacitor array sampling methods to reduce the change range degree of the comparator input common-mode voltage. Finally made an improvement of digital logic for reduce the delay time of the digital circuit ‘shift and register signals. When under the supply voltage of 1.2V, a sampling rate of 100Ms/s, the circuit simulation result show the SAR ADC achieves an SFDR of 78 dB, effective digit is 9.68 bits, post-layout simulation shows its SFDR is 68 dB, effective digit is 9.41 bits. Core landscape area is only 280 um x 130 um, with 3mw power consumption of the whole simulation, meet the basic requirements.