Embedded Memory And Computing-in-memory Circuits For Artificial Intelligence Applications

With the rapid development of artificial intelligence application technology,a large number of data transmission between CPU and storage circuit is recognized as the biggest bottleneck in the traditional von Neumann computer architecture.As one of the most successful algorithms for image recognition in the field of artificial intelligence,deep neural network needs to do a lot of multiplication and accumulation(MAC)operations for input data and weight data.The computing in memory(CIM)circuit can ont only support the general read write operations of memory circuits,but also perform a variety of operations,so it can greatly reduce the amount of data movement and further improve the energy efficiency of the system.The emerging memory and computing in memory circuit have a wide range of application prospects in high-efficiency artificial intelligence processor,Internet of things,smart home and smart city system,which are worthy of continuous in-depth research.In this dissertation,firstly,the development and typical architecture of computing in memory circuits are analyzed,including the classification and general read write operations of memory circuits,the bottleneck analysis of von Neumann architecture,the overview of deep neural network algorithm,and the advantages and disadvantages of early computing in memory research.Then,aiming at the challenges in the design of high energy efficient in CIM circuits,three kinds of high energy efficient CIM chips are proposed based on dual split control 6T(DSC6T)SRAM,twin-8T SRAM(T8T),and local computing cell(LCC).In the design of binary CIM chip based on split word line 6T static random memory unit(DSC6T),the main innovations include:(1)An in memory computing circuit based on DSC6 T is designed for two kinds of binary neural networks.(2)An asymmetric word line selection schemes is introduced to reduce the energy consumption of the system.(3)A dynamic input aware reference voltage gerneration circuit is proposed to adapt to different binary neural networks.In the design of multibit CIM chip based on twin 8T SRAM(T8T),the main innovations include:(1)A novel type of static random memory unit of compact twin-8T is designed.(2)An even odd dual channel input data mapping scheme is proposed to expand the data throughput of the system.(3)A weight data mapping scheme based on two's complement is proposed to reduce area cost.(4)A reconfigurable global local reference voltage generator with different bit-width precisions is proposed.In the design of multibit CIM chip based on local computing cell(LCC),the main innovations include:(1)A weight bitwise MAC operation supporting multibit operation is proposed.(2)A local computing cell is designed to resist the variation of process parameters.(3)A multibit reading circuit with low MAC read priority is proposed.On the basis of the above desing work,three SRAM based CIM chips were fabricated and tested to verify the innovative ideas in 65 nm,55nm,and 28 nm CMOS processes,respectively.The CIM design based on DSC6 T can support the full connected layer operations in two binary neural networks,and can achieve energy efficiency of up to 55.8TOPS/W.The CIM design based on T8 T can support input of 1-bit,2-bit and 4-bit,weight of 1-bit,2-bit and 5-bit,and MAC output of up to 7-bit.At the same time,this design can achieve energy efficiency of 37.5?45.36 TOPS/W.The CIM design based on LCC can support up to 8-bit MAC operations,can achieve 4.1ns to 8.4ns operation delay,and 11.5 to 68.4 TOPS/W energy efficiency.