An Computing In Memory Design Based On Double Word Line 9T SRAM

Intelligent electronic devices are developing in a more intelligent and refined direction.The data that electronic devices need to process is also becoming more and more numerous.The traditional Von Neumann computing structure can not meet the processing timeliness of the processor for abundant data.In order to reduce the problems between processor and memory caused by "memory wall",scholars put forward the concept of "computing in-memory ".Computing in memory is to processing data in memory to improve the amount and speed of data processing.It also reduces the power consumption caused by date moving between memory and processor.Static Random Access Memory(SRAM)has been widely used in cache with its advantages of fast read and write speed,low power consumption and easy integration.It has become the focus of computing in memory computing research.This paper proposed a dual word line 9T SRAM memory cell.The transmission transistor controlled by the word line is connected with the transmission transistor controlled by the storage node,and the other end of the transmission transistors controlled by the storage node is connected with the bit line to realize the read-write separation operation.When the proposed9 T SRAM memory cell performs writing operation,the bit line is precharged to a low level,and word lines are controlled to be turned on to write "1" and write "0" operations.In the Computing In Memory(CIM)mode,the proposed 9T SRAM can realize AND,NOR,XNOR and other logical operations and Content Addressable Memory(CAM)operations.During the CAM operation,the searched data is pre-charged to the bit line through the decoding circuit.When the searched data does not match the stored data,the match line will discharge.The sensitive amplifier detects the voltage change of the matching line to output the result of CAM.When performing the "AND" and "NOR" logic operation,two bit lines are precharged to the high level at the same time,and the "NOR" logical operation for data storage is carried out on the BL and the "AND" logical operation for data storage is carried out on the BLB.A sense amplifier is used to detect the voltage difference between the voltage on the bit line and the reference voltage to output the logical operation results.The XNOR logic operation can be realized by connecting the output of the sense amplifier of two bit lines in the same column to OR gate circuit.The proposed circuit is simulated in the 65 nm CMOS processed at 27 ?.The result shows that proposed computing model can complete the read,write and hold operations normally,the read noise tolerance is increased by 117% and 106% in the tt process angle and ss process angle,respectively,compared with the 6T structure.The CAM function verification of the a 64x64 array can realize the CAM function.The energy consumption test under the same array size saves about 40.46 times the energy consumption compared with the traditional calculation model.