The Circuit Design Of In-memory Calculation On 9T SRAM For Hamming Distance And Boolean Logic Applications

With the advent of the era of big data,autopilot,computer vision,speech recognition and other data-intensive applications are increasingly noticed.Nowadays,almost all advanced computing platforms are based on the famous von Neumann architecture,because of the separation of computing and data storage,frequent data transmission is needed between computing module and storage module when processing data,and this causes the problem of‘memory wall'.To dispose the problem of ‘memory wall',many scholars propose the concept of ‘processing in memory',which embeds part of the computing mode into the memory,so as to reduce the data transmission between the processor and the memory module.Static Random Access Memory(SRAM)is widely used as the cache of high performance processor because of its fast access.Its multi tube structure makes it possible to realize multi-function computing,which has been widely concerned by in-memory computing researchers.Nowadays,most of the research results based on SRAM in-memory computing are handling the column vector data in the storage array,that is,how to calculate the column vector in the array.However,the data in SRAM is stored by row,so these results may be limited in practical application.In this paper,a 9T SRAM cell structure is proposed,which can process both row and column data.It can read both row data and column data in the storage array,so as to realize different types of operations in memory.Based on the proposed 9T SRAM cell,in addition to the traditional SRAM mode,this paper also designs some other in-memory computing functions,such as approximate Hamming distance calculation of vector,logic operation of the row vector,matrix transpose read out and so on.Approximate Hamming distance calculation is to compare the binary data input from outside with the binary data stored in the storage array,and then outputting the analog voltage of two groups of data approximate Hamming distance.Logic operation is to carry out logic operation on two groups of storage words in the storage array,and finally output the accurate result of logic operation.Matrix transpose is to write the matrix into the storage array by row and read it out by column,so as to achieve the effect of matrix transpose.The size of the designed storage array is 128 × 128,and the simulation is under 65 nm CMOS process.Then,the calculation errors existing in the calculation mode are analyzed.The integral nonlinearity of Hamming distance calculation on row vector is less than 3.0 LSB,the integral nonlinearity of Hamming distance calculation on column vector is less than 6.7 LSB.Finally,the calculation power consumption in each calculation mode is compared and analyzed.The power consumption of Hamming distance calculation on row vector is 1.9 f J/bit,the power consumption of Hamming distance calculation on column vector is 3.8 f J/bit,the power consumption of logic calculation is 9.0 f J/bit,the power consumption of column read mode is 18.0 f J/bit.