Study Of Heavy Ion Irradiation Effects On CMOS And Non-volatile Hybrid Integrated Devices

The advanced integrated circuits?IC?with high integration and high performance present a bright future in the application field of aerospace.With the rapid development of IC technology,the new features and complexities have been emerged in irradiation effects for new type nanoscale devices,new material and new structure devices,hybrid integrated devices,heterogeneous integration and 3D integration devices.This thesis studied the physical mechanism of heavy ion induced irradiation effects in Complementary Metal Oxide Semiconductor?CMOS?and non-volatile hybrid integrated devices including Silicon-Oxide-Nitride-Oxide-Semiconductor?SONOS?technology Non-volatile Static Random Access Memory?NVSRAM?,thin/thick-gate-oxide anti-fuse Programmable Read Only Memory?PROM?and Flash-based Field Programmable Gate Array?FPGA?.The irradiation effects occurred in CMOS circuit modules and non-volatile circuit modules in these hybrid integrated devices were classified and analyzed in depth.Besides,the methods of radiation-hardened and potential space applications for these devices were discussed.For 130 nm SONOS technology NVSRAM,the irradiation effects of 6T SRAM cell?CMOS technology?and SONOS non-volatile cell were studied by using different species and energy heavy ions.The influence rules of heavy ion track structure,device supply voltage,ambient temperature and peripheral circuits on single event upset?SEU?occurred in 6T SRAM cell were achieved.On this basis,the mechanism of heavy ion track structure impacting multiple upsets was analyzed and the competition model of critical charge and collected charge under bias voltage was proposed.The SONOS non-volatile cell with upset threshold 60.9 MeV/?mg/cm²?presents a good irradiation tolerance.At the high linear energy transfer?LET?conditions,a few hard errors were observed in SONOS non-volatile cell,which decreased rapidly with time going and vanished completely in the end.This phenomenon is related to the annealing effect of heavy ion induced defects in SONOS transistor.For 130 nm thin/thick-gate-oxide anti-fuse technology radiation hardened PROM,the irradiation effects occurred in CMOS peripheral circuits including read/decoding circuits,control circuits and power management circuits have been studied by heavy ions.The upset types in buffer,register and address counter were classified and analyzed.At the high LET and high ion fluence condition,little hard errors are observed in anti-fuse non-volatile cell due to heavy ion induced the weaker breakdown of gate oxide in un-programmed cell than under the programmable voltage bias.The design of radiation hardened for this type device was analyzed,which indicated that the radiation tolerance of CMOS circuits can be improved by using redundant design,filter hardened circuits and latchup guard ring technology.In addition,the high reliability of data storage in anti-fuse non-volatile cell can be also achieved by implementing the redundant anti-fuse cells.For 220 nm Flash-based FPGA,the SEU sensitive areas of CMOS D-Flip-Flop?DFF?chains were scanned and imaged by high energy heavy ion microbeam,which showed that the high energy heavy ion microbeam can be applied in analysis of irradiation effects in large scale ICs.According to the logic configuration diagram of DFF chains and error data output technology with position feedback,the arrangement of logic tile in FPGA has been uncovered from the reverse analysis based on microbeam technology.The result shows that the physical distribution of logic tiles in FPGA has a high consistency with its logical arrangement.In ⁸⁶Kr ion experiment,the Flash switch cell and triple modular redundancy hardened DFF chains are all immune to SEU and SEL.Whereas for ²⁰⁹Bi ion experiment,the FPGAs after irradiation are not configured successfully because the write function of Flash switch cell is disturbed by heavy ion induced hard errors.The deep analysis shows that these hard errors are only occurred in the Flash switch cells without charge storage.