Study Of Single Event Effects And Hardening Strategies On Nanoscale SRAM-based FPGA

The SRAM-based FPGA with the advantages of reconfigurability and high performance has become the core electronic components of the space system.However,the logic states of the internal memories and registers of the SRAM-based FPGAs are controlled by the bitstreams,which are sensitive to the SEEs in radiation environment.The SEE induced failures can change the logic states of circuits,interrupt the functions,and threaten the safety of the on-orbit space system.The advanced space missions require high data storage,computing capability and performance of nanoscale SRAM-based FPGAs.However,these nanoscale devices are more sensitive to the heavy ion irradiation effects than the deep sub-micron devices.Therefore,this work focuses on the SEEs of SRAM-based FPGAs with 65 nm,28 nm,and 16 nm technologies.Based on the systematic heavy ion experiments and theoretical analyses,the failure thresholds and the physical mechanisms are investigated,and the laws of the radiation response of the nanoscale CMOS digital integrated circuits,the effectiveness and applicability of the hardening technologies are explored,providing the guidance and date supports for the radiation hardening design of the high-performance and high-reliability systems in the fields of aviation and aerospace.In this work,the testing method and system design for the SEE characterization of nanoscale SRAM-based FPGAs are investigated.The software and hardware implementations,vectors,modes,data analyses,fault diagnoses and priority of data extractions are introduced in detail.In addition,the physical mechanisms of the SEE responses of commercial SRAM-based FPGAs with bulk planar and Fin FET process are explored.The interactions between high-energy ions and nanoscale integrated circuits are discussed from both the device-level and circuit-level perspectives.Besides,according to the heavy ion accelerator experiments and simulations of Geant4,SRIM,TRIM and CREME,the influence of track profiles,energies and ranges are discussed.The SEU cross sections caused by different ions are affected by ion tracks and energies;the radiation sensitivities for different core resources such as CRAM,BRAM and DFF are different.Additionally,the configuration mode is also an essential factor which can affect the SEU sensitivities.The SEU cross section of BRAM increases by?10 times after an effective function configuration;a direct and significant correlation between the threshold of functional failure and SEU of CRAM is observed;with the help of the picosecond pulsed laser irradiation platform,the physical relation between the initial laser energy and the MBU of the Fin FET device is extracted,revealing the functional failures and potential risks for the space application of commercial Fin FET FPGAs.Based on the SEU cross section results,it is proposed and verified that the Al-foil degrader is rational and effective to be used to reduce the energy to complete the SEU sensitivity characterization and mechanism exploration of the flip-chip packaged devices when the high energy heavy ions are accelerated in ground test.Systematic researches on the radiation hardening effectiveness and failure mechanisms of nanoscale SRAM-based FPGAs with unit-level layout and circuit-level configuration hardening strategies are performed.The results show that the unit-level layout hardening strategy can reduce the SEU and MBU rates dramatically by alleviating the charge sharing effect,and the SEU threshold increase apparently from<5 Me V·cm²·mg^-1 to?18 Me V·cm²·mg^-1,indicating that the unit-level layout hardening is suitable for the?65 nm nodes to increase the threshold of the critical bit cells.The employed circuit-level configuration hardening experiments reveal that a combination of ECC and TMR hardening strategy can provide an outstanding effect to improve the SEU tolerance.Even for the high-LET ¹⁸¹Ta irradiation,the combination of ECC and TMR decrease the SEU cross section of the standard BRAM cell to 8.5×10^-9 cm²·bit^-1(reduced by?86.3%).The configuration hardening results for the 28 nm SRAM-based FPGAs confirm that the utilization of sensitive global clocks will cause×2 to×10 changes on the DFF SEU cross sections in square wave data pattern.Moreover,the CREME tools are employed to predict the on-orbit application of a specific SRAM-based FPGAs according to the particle spectrums in space environments,and it proves that the reasonable use of hardening strategies can effectively reduce the performance and area costs,but the physical layout hardening design for critical bit cells is still indispensable.A model proposed in this work is of great significance to evaluate the reliability of FPGA-based system.This model takes the system failures,critical factors and deep influences of multiple bit resources into consideration.The correlation and the impact coefficients between the critical CRAM bits and other resources,between the critical CRAM bits and circuit functions are important to guarantee the reliable operation of SRAM-based FPGAs in radiation environments.Multiple radiation hardened circuits based on the circuit structure of SRAM-based FPGAs are designed and fabricated using the 22 nm UTBB FDSOI technology and performed under heavy ion irradiation to investigate the radiation tolerance improvements of both the advanced process and customized hardening structures.The results show that the DICE units,single-port delay gates,dual-port delay gates etc.significantly reduce the SEU threshold and cross-section values.The SEU thresholds of the compact DICE and separate DICE units are?32 Me V·cm²·mg^-1 and?37Me V·cm²·mg^-1,respectively.The influence of the transient pulse disturbance at the 22nm circuits is nonnegligible.In addition,the hardened circuits are easy to be affected by the back-bias voltage of the device.A slight variation of back-bias voltage(±0.2 V)can cause an increment in SEU cross sections,mainly due to the impact of the changed threshold voltage and the carrier collection procedure.Considering the existence of 4?-distributed relativistic heavy ions in space,the large-tilt irradiation is performed,and the failure conditions of the hardened circuits,charge ionizations,energy loss and depositions are obtained in large-tilt high energy heavy ion irradiation,which are significantly different from the data of low-energy ion vertical irradiation.The results indicate that merely based on the vertical irradiation may overestimate the radiation tolerance of devices.Furthermore,our irradiation results verify that it is feasible for the future SRAM-based FPGAs to achieve super radiation tolerance by using the FDSOI technology.The relevant experimental results can provide data support and design guidance for the development of space-grade radiation hardened devices with the feature size below 22 nm.