Single Event Effect Simulation And Hardening Design For SiC Power VDMOSFET Devices

Compared with Si-based devices,SiC power VDMOS(Vertical Double-diffused MOSFET)devices have become an important device for the development of high-temperature and high voltage devices,and have very great material advantages and broad application prospects in various application fields.In the field of space applications,semiconductor devices will be affected by cosmic radiation,causing device failure.The research on the single-event radiation effect and radiation hardening technology of SiC power VDMOS devices is are the main focus of current research.This article will focus on the simulations and radiation hardening design of SiC power VDMOS devices.The following are the main research contents and results:(1)The basic theory of SiC power VDMOS devices is studied,which provides a theoretical basis for the development of single-event irradiation simulation.Firstly,the physical models used in single-event irradiation simulations are studied,including drift-diffusion model,bandgap model,mobility model,impact ionization model,incomplete ionization model and carrier recombination model.Secondly,the single-event burnout model and single-event gate-rupture model of the device were studied in detail.It is found that the main mechanism that causes single-event burnout of SiC power VDMOS devices is that the parasitic BJT inside the device is triggered,and the amplified current is generated,which causes the device to be burned out.The charge accumulation caused by particle incidence increases the electric field and leads to breakdown,which is the main reason for the single-event gate rupture for the device.(2)Simulation and analysis the single event effect of SiC power VDMOS devices.First,the static characteristics of the device rated at 1200 V are simulated,including conduction,transfer and breakdown characteristics.The simulation results show that the device has a threshold voltage of 2.4V and a breakdown voltage of 1442 V.Then,the simulation analysis was carried out by changing the particle characteristics,the bias conditions and the structural parameters of the device.And,the influence of these parameters on the single event effect has been studied systematically.The simulation results show that the external drain voltage is the key factor for the single event effect when the device is switched off.When the device is irradiated with thallium particles,the burnout threshold voltage of the device is 497 V.The variation of the burnout threshold of the device is mainly affected by the the LET(Linear Energy Transfer)value.When the LET value is increased from 0.5p C/micron to0.9p C/micron,the burnout threshold will be reduced by 92 V.The single-event gate rupture effect is not sensitive to most device structural parameters.(3)Radiation Hardened By Design(RHBD)techniques of SiC power VDMOS device.Two hardening methods namely,the body expansion design and the buffer layer design have been proposed in this thesis.The simulation results show that the effect of body expansion design on improving the single particle resistance of the device is weak,and the burnout threshold voltage of the device can only be increased by 3%;The buffer layer design can effectively improve the single particle resistance of the device.With a thickness of 1?m and uniform buffer layer with a doping concentration of 1×1017cm-3 used in simulations,the device burnout threshold can be increased to 891 V,an increase of 79%,and the static breakdown voltage of the device will be reduced to 1252 V.In order to further improve the device,we proposes a design that replacing the uniform doping of the buffer layer with Gaussian doping.The simulation results show that the use of a Gaussian doped buffer layer can increase the burnout threshold voltage to 1028 V,an increase of 106%,and the static breakdown voltage is still upto 1225 V,which can still ensure the normal operation of the device.