The Study Of Single Event Effect And Hardening Technique In FDSOI Circuits

Fully depleted silicon on insulator(FDSOI)device,as a new type of device structure,has attracted more and more attention in the integrated circuit industry due to its excellent radiation resistance,low voltage and low power consumption.However,the critical charge of Single Event Upset is reduced with the shrink of process size of the FDSOI device and circuits.And the buried oxide layer is gradually thinned to increase the influence of the back gate radiation effect.Therefore,it is of great theoretical and practical significance to clarify the mechanism of Single Event Effect in the device and circuits of nano-scale UTBB FDSOI,and to carry out targeted research on the hardening technology on this basis.In this paper,the Single Event Effect simulation analysis and the hardening technology study work of FDSOI technology are carried out from two aspects of the device level and circuit level.The main research contents and results are as follows:1.A 28 nm NMOS FDSOI three-dimensional device model was built using Sentaurus simulation tools.The Single Event Effect mechanism of FDSOI device was simulated and analyzed,and a double exponential current source model containing Gaussian correction terms was established for the obtained transient current pulse.Comparing the current and voltage characteristic curves of the built device model and the SPICE model,the two curves are in good agreement.By changing the incident position,LET,drain bias,back gate bias and other conditions of the Single Event Effect simulation,the influence mechanism of each condition on the Single Event Effect transient current is analyzed.The results show that the transient current pulse of the Single Event Effect is mainly affected by the amount of charge ionized by the particle incident and the electric field collecting the charge.Because the buried oxide layer of FDSOI device isolates the charge collection of the substrate,the transient current pulse drops faster.Using the comparison method of setting different particle incident lengths,the influence of back gate on transient current is mainly studied.The results show that the motion of radiation-ionized carriers in the substrate changes the potential of the back gate,thus affecting the charge collection at the drain.The increase or decrease of the potential depends on the doping and potential distribution of the substrate.If the potential increases,the peak value of the current pulse increases;while the potential decreases,the peak value of the current pulse decreases.Considering the influence of the back gate of FDSOI device,the obtained current pulse isfitted with an improved double exponential function,and the Gaussian term is added to modify the charge collection process to establish a transient pulse injection model suitable for FDSOI devices.The fitting results show that the maximum error of the peak current of the fitting curve is less than 1%,the maximum error of the total charge quantity is 4.16%,and the maximum error of the pulse full width at half maximum is 6.71%.The revised model improves the peak position and tail of the pulse,the peak error is reduced,the time to reach the peak is closer to the original pulse,and the tail is weakened.The double exponential function model with Gaussian correction term solves the problem of the traditional double exponential model underestimating the peak current.2.Based on Verilog-A language,the established current source model is described as a pulse injection model that can be identified by circuit-level simulation.Using this model,the problems existing in the Quatro hardening structure are analyzed,and then two improved radiation hardened methods are proposed,which are based on resistance partial voltage and back gate modulation.The detailed principle analysis and simulation study of two hardened methods are carried out for SRAM cell and D flip-flop composed of Quatro structure,respectively.The results show that the upset resistance of the SRAM circuit based on the resistance voltage division method increases by 74%,and only 2 transistors are added.The power consumption and delay time increase by 22%,24.6%,respectively.And the upset resistance of the D flip-flop increases by 58.3%,and only 4 transistors are added.The power consumption,setup time and delay time increase by 10.8%,12% and 8%,respectively,which are all about 10%.The upset resistance of the SRAM circuit based on the back gate modulation method increases by 3.7%.And the upset resistance of the D flip-flop increases by 5.5%,the power consumption and delay time are basically unchanged.