Study Of Single Event Effects On SRAMs And MRAM Devices

The development of integrated circuit technology provides unlimited possibilities in terms of spacecraft devices.At the same time,it also proposes new challenges to the reliability of advanced circuits in the radiation environment.Therefore,we have studied the single event effects(SEEs)on the advanced nano integrated circuits,which are of great significance for establishing physical models of radiation damage and guiding the development of radiation hardened technology.Based on the advantage of high-energy heavy ions provided by the Heavy Ion Research Facility in Lanzhou(HIRFL),we have investigated the SEEs in SOI SRAM,3D SRAM,and MRAM induced by the heavy ion irradiation under different ion species,energies,fluences,under different pre-irradiated dose and layout structures.In this paper,we have explored the physical mechanism of the radiation damage in advanced nanodevices and noncharged storage devices induced by heavy ion irradiation.We then obtained a physical model of change,degradation,and failure of the electrical state caused by the disturbance of ionized charges or the accumulation of microscopic damage.The impact of the ionization radial profile of an incident ion on the single event upset(SEU)in nano-devices has been studied.The effects of heavy ion species and the energies on SEU cross-section(CS)of 6T and delayed filter-reinforced(7T)SOI SRAM were analyzed.The results show that the saturation CS of a 6T SRAM has significant dependence on the heavy ion species,with a maximum difference of up to 200%.The saturation CS per bit of the 6T SRAM is twice as high as the sensitive region of the off-state transistor,confirming that the ionization track substantially enlarges the sensitive area of the nanocircuit.When the energy of 181Ta ions increased from 3.7 MeV/u to 8.3 MeV/u,the SEU CSs of 6T and 7T SOI SRAMs were increased by twice and two orders of magnitude,respectively.The results show that the ionization radial profile of ion tracks significantly affects the SEU-CSs of nanotechnology layout-hardened devices.Regarding the impact of layout structure on SEU in nanodevices,the sensitivity difference between delay filter reinforcement and 6T structure has been investigated.When the heavy ions had normal incidence,hardening the 130 nm 6T structure by single-gate transistor filtering(7T),the LET threshold of SEU was one order of magnitude higher than that of a 6T structure.And the saturation CS was one order of magnitude lower than that of the 6T structure.For the 22 nm 6T structure with double-gate transistor filtering(8T)hardening,the corresponding SEU threshold increased 24 times,and the saturation CS decreased 0.5 times.The results showed that the sensitivity of devices with delay filter hardening techniques can be significantly improved.When the incident angles of the 1811Ta ions increased to 40 degrees along the bit line,the SEU-CSs of the 130 nm 6T and 7T SRAMs increased by 17.7%and 157.2%relative to that of normal incidence,respectively.When the 86Kr ions incidence along the word line and bit line of devices,respectively,the variation of SEU-CS of 130 nm 7T SRAM at 56 degrees achieved one order magnitude,and the variation of SEU-CS of 22 nm 8T SRAM at 80 degrees achieved four times.The experimental results showed that the reason for the discrepancy is that the probabilities between the delay filter transistor and a sensitive node disturbed by the ionized charge simultaneously are different under different angles.The impact of the total ionizing dose on the SEU in the nanometer SOI SRAM has been studied.And the sensitivity difference of layout structure circuits on SEU as a function of TID was obtained.When pre-irradiated to the dose of 800 krad(Si),the SEU-CS of the 6T SRAM increased about 15%,and that of 7T SRAM decreased 60%.Under the TID pre-irradiation,for the first time,the different trends of SEU-CS in terms of layout structure were observed,which was attributed to the RC delay rise induced by the accumulated trap charges in the radiation hardened circuits.The impact of the spatiotemporal evolution of heavy ion ionization tracks on SEU in 3D SRAM has been explored.We investigated the effects of the ion energy,the location of the Bragg peak,and the vertical spatial distribution of the sensitive volume on the SEU sensitivities of SRAM in different tiers.A significant range effect was observed in the simulation calculations.The difference between SEU-CSs under different ranges was up to two orders of magnitude in the ascending region and was up to double in the saturation region.The intrinsic relationship between the variation of CS in different tiers of 3D SRAM and the time evolution of ion tracks has been revealed.A physical model and a critical range formula of the maximum SEU-CS have been proposed,and further development of a practical test method for quantitatively evaluating the SEU-CS of 3D SRAM.In addition,the accuracy of this test theory has been verified by the 100 MeV/u 209 Bi experiments.Regarding the impact of high-energy heavy ion radiation damage on the macro-electrical functions in MRAM devices,we studied the principles of the MTJ s electrical properties affected by the ion species,energy,LET,and fluence.In the high-energy 181Ta irradiation experiment,for the first time,the failure of MTJ electrical function,induced by radiation damage,was observed,and 79.9%of that was due to high resistance state failures.The resulting calculations showed that the micro damage induced by multiple heavy ions was the key factor of MTJ electrical function failure.We have also observed that the MTJ damage performs annealing characteristics at room temperature,and that increasing temperature can accelerate the annealing,which suggests that the thermal vibration of the lattice atoms was the intrinsic mechanism for the repair of defects.A physical model of the MTJ macro high resistance state degradation induced by the micro damage of the insulating barrier layer was proposed by combining y irradiation experiments and simulations.