Research On Key Technologies Of Reconfigurable Cryptographic Processors

In order to improve the security for special secure communication,the cryptographic algorithm needs to be changed frequently.Thus the cryptographic processor needs to be compatible for multiple algorithms.Compared with specific integrated circuits and application-specific instruction-set processors,coarse-grained reconfigurable processors have potential advantages in both performance and flexibility,and thus have become one of the hottest issues in academia and industry.In order to improve the energy-efficiency and the area-efficiency of the reconfigurable cryptographic processors,this thesis focuses on the computing array architecture,circuit design and configuration scheduling mechanisms.First,this paper analyzes the working mechanism of cipher algorithms,such as block cipher algorithm,hash cipher algorithm and stream cipher algorithm;the computing features of the algorithm are summarized from three aspects: the key length,the computing bit width and the operation types;analyzes the control flow characteristics of the algorithm including the data dependence within the iterative operations and DFGs.Secondly,this paper proposes a lookup table(LUT)structure based on the multi-port static random access memory(SRAM)to solve the problem of low area efficiency caused by the excessive consumption of S-box(Substitution Box)in computing arrays.The main research work include: 1)a multi-port SRAM based LUT structure is proposed.By configuring this LUT with specific parameters,it can be used to meet different requirements of the input and output bit width,the number of LUTs and the access concurrency features of various cryptographic algorithms;2)the multi-ports SRAM memory architecture is designed,which supports one writting port and four reading ports.This structure is suitable for the operation characteristics of large number of concurrent reading operations and low frequency of data updating operations in S-box.It can provide greater read data throughput,so as to meet the requirement of high concurrent access to the memory of the LUT by the S-box operations.Compared with other approaches,with the proposed lookup table structure,the data throughput per unit area is increased by upto 51.76%.Thirdly,the area efficiency and energy efficiency of the processor are usually low,since the computing pipeline is often blocked by the configuration procedures.In order to solve this problem,this paper: 1)proposes a configuration organization method based on basic operations and a multi-level organization structure of configuration.With these approaches,the storage can be reduced by more than 82.25%,while ensuring the configuration transmission efficiency;2)propose a scheduling mechanism which takes into account the temporal locality and spatial locality of the configuration context.With this approach,the percentage of configuration time in the total computation time can be reduced to 4.35%~8.78%,with less extra hardware overhead.Finally,the techniques discussed above are applied to a reconfigurable cryptographic processor.The chip implemented based on the SMIC 40 nm process.The experimental results show that the area and energy efficiency of the reconfigurable cryptographic processor have been improved significantly.1)the multi-port SRAM lookup table structure reduces the area of the reconfigurable cryptographic processor by 11.81%;2)based on the scheduling mechanism of configuration context,the configuration time is reduced and the performance is improved.Compared with other designs,by adopting the approaches proposed in this paper,the reconfigurable cryptographic processor can support more cryptographic algorithms.Moreover,for the block cipher algorithm(e.g.AES),the area efficiency is improved by 2.09 ~ 4.63 times,the energy efficiency is improved by 1.07 ~ 4.53 times;for the hash cryptography algorithm(e.g.SHA256),the area efficiency is improved by 2.91 times;and for for the sequential cryptography algorithm(e.g.ZUC)the area efficieny is improved by 2.80 times.