| Currently, delay-locked loops (DLLs) and phase-locked loops (PLLs) are too large and inefficient for extensive use as clock-alignment circuits in complex ICs. Their area tends to be dominated by the loop-filter, which requires large capacitors that scale proportionally with the loop-gain. With advances in technology, supply swings are reduced and the sensitivity of the loop must increase, requiring larger filters that often make fully integrated solutions impractical.;Using this structure a very compact low-power PLL was implemented in 0.18mum CMOS for clock management and distribution. Like digital PLLs, it is composed of standard-cells, can be mixed with regular logic, and is digitally placed & routed, but unlike digital PLLs it does not suffer from quantization jitter. Its area is only 0.008mm2 (650 'gates') when configured as a x32 clock multiplier with a 200kHz loop-BW. In this configuration, it consumes only 190muW 128Mhz. It can perform efficient clock distribution, cleansing a noisy low-frequency reference and synchronizing outputs with cycle-to-cycle jitter below 5.6ps rms. With a lock-range between 60-172MHz, adjustable loop dynamics and last lock frequency memory, it is less than 1/5th the size and 1/15th the power of previous PLLs at similar frequencies and noise levels.;In this work a new cascaded charge-pump (CCP) and dynamically rotated filter structure are introduced to replace the conventional charge-pump. The cascaded charge-pump can be formed with digital tri-state buffers, but connected in such a way that they act as a network of small and simple analog charge-pumps. The structure generates a thermometer-coded vector of analog control voltages to modulate a voltage-controlled oscillator (VCO) or delay-line (VCDL). By implementing the VCO control with a vector, rather than a single voltage, the VCO gain/node (KV) can be arbitrarily reduced. The reduction in KV creates a corresponding reduction in capacitive requirements, making the circuits far more area efficient. |
