Researches On Data Protection Technique Of Submicron VLSI Based On Redundant Residue Number Systems And Equalization

Due to the advanced process technologies, such as shrinking of feature sizes, increasing die sizes, scaling of supply voltage, increasing interconnect density, faster clock rates, reduced nodal charge and reduced device spacing,lots of submicron effects must be considered in the submicron VLSI designs. And these effects bring the challenges for data protection in the submicron VLSI designs, particularly in these two aspects:(1) the soft errors caused by Single Event Upsets(SEUs) and Single Event Transients (SETs) in radiation environments; (2) the data protection for on-chip data transmission. The researches in the dissertation mainly focus on these two issues.For the data protection issue in radiation environments, we define the Soft Error Tolerant Calculation Systems (SETCS) and introduce Redundant Residue Number Systems (RRNS) to the area of Radiation Hardening by Design (RHBD). Based on RRNS, a novel hardening scheme is proposed for radiation hardening for the datapath in Chapter 3. The proposed hardening scheme employs redundant residues to mitigate soft errors. We use the properties of RRNS, such as independence, parallel and error correction, to establish the radiation hardening architecture for the datapath in radiation environments. In the proposed architecture, all of the residues can be processed independently, and most of soft errors in the datapath can be corrected with the redundant relationship of the residues at correction module, which is allocated at the end of the architecture. There is not any additional processing in the architecture but correction operation and binary to residue translation. Thus, the proposed scheme has high efficiency when the processing steps of the datapath are large. In order to provide protection for the key module in the proposed scheme, correction module, some traditional protection methods, including Guard-gate Register Triple Modular Redundancy (G-RTMR), pipeline-level TMR, and module-level TMR, are used to construct the hybrid protection schemes. In the case studies, we find that the RRNS based scheme and the hybrid schemes can reduce soft error rate (SER) from 10-12 to 10-17, 10-18, 10-25, and 10-25, respectively, only with 45.6-46.1% area overheads and negligible latency overheads, when the pipeline stages of datapath are 10 4 and the moduli set with correction capability of one residue is adopted. The case studies also show that the proposed schemes can achieve less area and latency overheads than that of the datapath without radiation hardening, because RRNS can reduce the complexity of operations in datapath.Single Event Multiple Bit Upsets (SEMBUs) is one of the major challenges of the data protection issue in radiation environments at the modern and future process technologies. In Chapter 4, we extend the work in Chapter 3 and propose a joint scheme RRNS and module isolation (MI) to mitigate SEMBUs for the datapath in radiation environments. The proposed hardening scheme employs redundant residues to improve the fault tolerance for the datapath and module spacings to guarantee that SEMBUs caused by charge sharing do not propagate among the operation channels of different moduli. In the proposed scheme, all of the residues can be processed independently, and most of the soft errors in the datapath can be corrected with the redundant relationship of the residues at correction module. In the back-end implementation, MI technique is used to improve the soft error rate performance for RRNS with physically separating the operation channels of different moduli. The case studies show that an order of magnitude decrease on the soft error rate (SER) as compared to the NonRHBD designs can be achieved at least, and that RRNS+MI can reduce the SER from 10-12 to 10-17 when the processing steps of datapath is 106 . The proposed scheme can even achieve less area and latency overheads than that without radiation hardening, since RRNS can reduce the complexity of operations in the datapath.Error correction algorithm is the key for the RRNS based hardening schemes . In Chapter 5, we explore the new feature of RRNS and DSP systems-the relationship between the minimum distance of RRNS and the practical integer range of DSP systems which is represented with binary number systems (BNS). With this relationship, we get that for a given RRNS, any two residue moduli have the same correcting capability. Thus, we optimize the algorithm presented in [25] with the optimal residue moduli for single error correction algorithm. The proposed algorithm chooses the optimal residue moduli for single error correction. Thus, it has a reduced implementation and computational complexity than that of [25]. Proofs and case studies are provided for the proposed algorithm.For the data protection for on-chip data transmission, we propose an effective equalization scheme in Chapter 6. We develop a new joint scheme which integrates an equalization technique and special spacing rules for improving the speed and reliability for VLSI on-chip communication buses. The proposed equalizer employs a variable threshold inverter whose switching threshold is adjusted as a function of the past output of the bus. The experimental results of a 10-mm 32-bit bus in 0.13-um CMOS process technology show that 1.28 speedup is achievable by equalization alone with 1% area overhead. The simulation results also show that the joint equalization and increasing spacing of the uncoded bus can reduce 50% delay and save 42% power only with 52% area overhead compared with the minimum-spaced uncoded bus. The Bit Error Rate (BER) of the bus can be improved from 10-5 to 10-24.