Single Event Upsets Hardened By Design Technology Research Of Static Random Access Memories

For static random access memory(SRAM), changes associated with the evolution tocomplementary-metal-oxide-semiconductor(CMOS) integrated circuit technology havehad a dramatic influence on the radiation effects due to ionizing effects of atmosphericneutron, proton, alpha-particle, and cosmic rays in space and terrestrial environments.As a result, multiple cell upsets(MCUs) and multiple node upsets are becoming majorissues in the reliability of SRAM memories. Therefore, radiation hardened technologiesin fabrication processing, design and layout procedures all require continued modificationto accommodate further scaling. For the time being, radiation hardened by design(RHBD)of commercial SRAMs memories is a major hardening method, because it is compatiblewith standard commercial CMOS process, i.e., it do not require extra process steps tofabricate integrated circuit(IC) chips. In this paper, we present various RHBD techniquesthat have been used to mitigate single event upsets(SEUs) at the system-level and circuit-level for hardening CMOS SRAM memories. The major contents of the work include:(1) To correct transient MCUs in SRAM memories, more complex ECCs are widelyused to protect memory, but the main problem is that they would require more overheads.In this paper, decimal matrix code technologies are proposed for hardening SRAM mem-ories, novel decimal matrix code(DMC) based on divide-symbol is designed to enhancememory reliability with lower overheads. Firstly, the word is divided into some symbols,and then these symbols are arranged in a 2-D matrix; secondly, decimal integer additionis performed for obtaining the maximum error detection capability and binary operation isperformed for minimizing the overhead of encoder and decoder. Simultaneously, in orderto reduce the area overhead of decoder, we have used the ERT in which the encoder isalso reused for obtaining the syndrome bits in decoder. As a result, it can reduce the areaoverhead of ECC without disturbing the whole encoding and decoding processes, i.e., inthe encoding(write) process, the encoder is only an encoder to execute the encoding oper-ations. However, in the decoding(read) process, this encoder is employed for computingthe syndrome bits in the decoder. Finally, the obtained results showed that the proposedscheme has a superior protection level against large MCUs(5-bit) in memory;(2) One-step majority logic decodable(OS-MLD) codes that can correct MCUs area good choice due to low complexity and latency. However, these codes need more re-dundant bits, i.e., they have not stored more information bits. This paper proposes novelmixed codes(MCs), which are constructed by doubly transitive invariant(DTI) and Ham-ming codes, to mitigate MCUs in common memories with lower overheads and highercode rates. Firstly, the puncturing technique is used to increase the code rates of the pro-posed codes so that more information bits can be stored in memories. Then, in order toreduce the average latency of the decoding process, we have proposed the error detectionmodule using the proposed ERT technique so that read operations are accelerated. Finally,as an application example, a(64, 42) double error correction(DEC) MC is evaluated andcompared with the existing DEC codes. The results obtained show that the proposed MCwith higher code rate can not only effectively mitigate MCUs in memories but also reducethe overheads of the memory cells;(3) The main theory behind multiple code upsets in SRAM memories due to nor-mally incident particles is called charge sharing that means the spreading of the depositedcharge by diffusion. As the CMOS process technology continues to scale to the nanome-ter regime, the effect of charge sharing induced by an angled particle is becoming moresevere. Therefore, traditional radiation hardened memory cells have been facing a seriouschallenge against increasing multiple-node upset, so that the underlying trend is to requirenew hardening memory design for considering the multiple-node upset. In this paper, twonovel radiation hardened memory cells(RHM-N and RHM-P cells) with 12 transistors areproposed which utilizes the SEU upset polarity(when a radiation particle strikes PMOStransistor, only a positive transient pulse is generated; on the contrary, when a radiationparticle strikes NMOS transistor, only a negative transient pulse is induced) and transistorlayout method to provide fault-tolerant capability. The radiation hardened cells we haveproposed have advantages: the ability to tolerate an SEU in any single sensitive node,the ability to fully tolerate a multiple-node upset regardless of the stored value of mem-ory cell, an SEU tolerance capability even under the impacts of process variations, and alow-power consumption.As we enter the 21 st century, RHBD technologies are becoming a good radiationhardened technology to reduce the cost for hardening integrated circuits. However, thehardened technologies for mitigating MCUs and multiple code upsets in SRAM memoriesstill have to face a lot of problems. In this paper, the proposed RHBD technologies withwith high-reliability and low-redundancy advantages for hardening SRAM memories are agood choice for solving these problems, which is of great importance for the developmentof our country’s aerospace.