Research On Cmos Storage Cell Circuits Design For Single Event Upset Tolerance

There are a mass and variety of particles in space environment.When Integrated circuits are exposed to space environment,these particles may hit on the ICs leading to radiation effects,such as single event upset,single event latchup and single event burnout and so on.These radiation effects will deteriorate the performance of ICs or even fail them.As an indispensable part of electronic system and the carrier of large amounts of data,single event upset occuring on storage circuits in radiation environment has become an important factor that endangers the stability of chip system.For example,European Space Agency once has reported the satellite crash event due to single event upset.So it is very important to harden storage cell against single event upset.Radiation hardened by design(RHBD)is a popular design method for radiation hardening,because it promises to improve the performance of rad-hard ICs by utilizing state-of-the-art commercial foundry silicon processes and reduces the cost of manufacture.In this paper,Static Random Access Memory Cell(SRAM),latch and D-flip-flop,which belong to storage circuits,are hardened by RHBD,and the major contents of this paper including:(1)Research on radiation hardened SRAM cell design against multiple-node upset.As the internal storage module,SRAM occupies a large proportion of chip area,so the single event upset tolerance ability of SRAM directly affects the performance of the whole system.In this paper,a radiation hardened by desgn 12 T SRAM cell based on redundant hardening is proposed(RHD12T cell).According to the structural characteristics of RHD12 T,some nodes of RHD12 T are further hardened at layout level.Simulation results show that,with the help of circuirt level and layout level hardening technique,RHD12 T cell can tolerate single event multiple node upsets,no matter particles at normal or angle strike.(2)Research on radiation hardened low power latch design against SEU.As the minimum unit of a sequential circuit,the single event upset tolerance ability of latch circuit in space environment directly affects the correctness of data processing in sequential circuit.In this paper,a low cost radiation hardened latch based on double modular redundancy is proposed(LCRH latch)to tolerate SEU,and it also feature low power consumption.Besides,some part of LCRH latch cell can be reused,this special design makes LCRH latch filter SET in high level clock and prevent the output node taking a high impedance state on output node when SEU occur on some of its internal nodes in low level clock.Simulation results show that,compare with the latches which have the same error tolerance ability,LCRH latch has low power feature.(3)Research on radiation hardened D-Flip-Flop design for pipline application.In this paper,based on the principle of detect and correct technique,a novel transition detector(NTD)is proposed.Based on NTD circuit,a novel soft error tolerance D Flip-Flip(NFF)is structured.The proposed NFF not only can detect SET and timing error(TE)during transmission mode,but also can detect and correct SEU during hold mode.Simulation results shows that,compare with SETTOFF which has the same fault tolerance ability,the proposed NFF has effectively reduce the width of the correction giltch.littler correction glitch means the probability that the downstream sequential circuits capture the correction glitch goes down.This further reduces the rewrite frequency of pipeline,which finally increase the speed of pipeline and reduce power consumption.(4)Research on radiation hardened SRAM cell design against multiple-node upset for near-threshold Application.Due to the limitation of energy carry during deep space exploration and the requirement of low power or even ultra-low power applications in medical electronics and mobile terminals,this paper has proposed a radiation haredned near-threshold SRAM cell to tolerate single event multiple node upset.Details are as follows: based on redundant hardening and polarity hardening technique,a radiation hardened by design near-threshold SRAM cell(RHDNT cell)is proposed at circuit level;After that,in order to obtain the ability of tolerating multiple nodes upset,further hardening design has been done at layout level to isolate node pairs.Simulation results show that,RHDNT cell can tolerate SEU,and can read and write stably.Besides,it also has a higher read and write SNM.Using RHBD technique,this paper studies storage circuit design under CMOS process,and gives correspoding design schemes of radiaiton hardened SRAM,latch and DFF.These design schemes all have high practical value in aerospace industries.