Single-particle Effect Mechanism Of Multi-well Process In Nano-CMOS Devices

With the rapid development of aerospace science and technology in China,the integrated circuit systems have been widely used in the field of aeronautics and astronautics,and the feature size of chip manufacturing process steadily decreasing has propelled the single-event effect(SEE)which induced by heavy-ion irradiation as the primary factor which affecting the reliability of the aerospace control systems.The charges in circuit storage nodes is decreasing while the CMOS device technology into nano size,and the critical charge to represent a logic state upset propelling the semiconductor devices reliability increasing for the heavy-ion radiation.Thus,single-event multiple-node upset has become a major performance induced by the charge sharing which occurred in nano CMOS devices.At present,the different well technology has a great influence on charge carrier transport models,thus the studies about multiple-well deserve more attentions.According to the mechanism studies of the nano CMOS devices have strong theory instructive affects on SEE radiation hardening,this paper have studied respectively from the physical level models,device level simulations and circuit level hardened tests to research the SEE of the nano CMOS multiple well devices detailedly,and the study results are listed as follows:(1)The Monte-Carlo based SRIM simulation program is adopted to track the process of energy loss when a certain number of high energy helium ions are striking into the silicon materials.According to fitting the ionization damage distribution in the silicon material,it is found that the energy losses of heavy-ions in shallow silicon region are the largest,and the silicon ionization is the most remarkable,and these verified that the charge agminated region will provide a large amount of charge for the sensitive nodes of the shallow silicon devices.Fitting the 3-D distribution data of the helium ion ionization energy to generate the Prague curves of average ionization energy versus incident depth,provides a conversion equation for the heavy-ion linear energy transfer in silicon improving the feasibility for the numerical simulations using LET values directly.(2)Through TCAD numerical simulation software to built the dual-well CMOS devices for analyzing carefully the transient pulse current transmissions and the upset voltage outputs of NAND gates,have studied the major components of transient current pulses on 3-D dual-well SRAM cell and evaluated the collected charge on PMOS transistor.Firstly,the small signal circuit models are implemented to explore the transient charge sharing effects on(3)adjacent PMOS.Furthermore,the accurate amplitudes and pulse widths of 3-D inverter output voltages have been induced to explain the mechanisms of SET pulse transmission,and provides the compared references for 3-D triple-well device hardening designs.(3)This component has intensively studied the SETs on triple-well process devices and mechanisms of charge collection.The differences of SET current pulses and charge collection on triple-well SRAM cell and the corresponding dual-well SRAM cell have been studied in detail,and the contributed charge collection volume for single-event upset is calculated quantitatively.The study results show that the triple-well guard-ring contact hardening design can effectively reduce the amount of device charge collection,and charge reduction can reach60% than collected charge in dual-well device,thus the parasitic bipolar amplification effects in triple-well devices could not contribute collected charge significantly,indicating that the triple-well guard-ring contact well layout is feasible in radiation hardening design.(4)Adopting HSPICE circuit simulation software to setup the injected pulses simulations in improved D trigger logic circuits.Based on the analysis of the response characteristics of transient currents in the hardening and un-hardening D trigger logic circuits,and circuit level simulations show that the output buffer circuit has good mitigative effects on output electrical level response of the transient currents,thus the topological buffer circuit module can provide technical references for the design of the radiation hardened circuits.