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Research On Peripheral Modules Of Single Chip Micro-Computer

Posted on:2009-02-21Degree:MasterType:Thesis
Country:ChinaCandidate:J H ZhouFull Text:PDF
GTID:2178360272457233Subject:Microelectronics and Solid State Electronics
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This thesis adopts the"Top-Down"method to design the peripheral devices modules of HP-51 MCU which compatible with the Intel MCS-8051 MCU. The author selects the Modelsim as the functional simulation software and the Synplify PRO as the synthesizer software and Quartus as the FPGA developing platform. All the tasks such as writing sourse code, functional simulation are completed in the software environments.At the last, synthesized the design on the Altera Cyclone chip, and completed the front sorce code design of the peripheral modules.Firstly, the thesis introduces the history of MCU,implementation orientation,developpment trends and the common methods of design very large scale digital integrated circuits; then introduces the HP-51's architecture characteristics,instructions aggregate,interrupt systems, last author analyzes the peripheral modules'function,architecture and the working mode of the HP-51 MCU in detailed. In this thesis author explans the processes of design Serial Communication Interface and Timers detailedly, including lists the I/O ports of every Sub-functional modules, some source code, detailed functional simulation waveforms and synthesized RTL-level circuits.There are two improvements for the traditional serial communication port in this thesis: firstly, eliminate the noise from serial lines before the serial data is sent to the serial interface; then the serial data is sent to a autotuning baud rate generator, the baud rate is detected automatically and the baud rate divider can be sent to the control register. At last the pure serial data is sent to the serial interface. These two improvements can enhance the serial interface performance.And they are the innovative points in this thesis.Use Verilog HDL to write source code, do enough simulation and verification in the design process is the typical methods of design VLSI. All the design ideas which are adopted in this thesis are all encolsed to the valid-functional, reusable and transplantable properties. Use HDL to design electronic systems is a very popular method in recent years, It is very suitable for describing the very large scale digital ICs, especially used in the SoC design process. The peripheral modules designed by this thesis has very good re-usable properties, they can be used in other similar designs with few changes.
Keywords/Search Tags:Hardware description language, Universal Asynchronous Receiver Transmitter, Asynchronous communication, Field Programmbale Gate Array, Serial Communication Interface, Timers
PDF Full Text Request
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