Research On Low Power Design For NoC

To improve the performance of electronic system efficiently, SoC is evolving towards integrating thousands of IPs, for which traditional bus ahrchitectures are not suitable due to poor scalability and low bandwidth. For this reason, pipelined, packetized NoC is being proposed for complex SoC.Such solution provides high scalability, and increases interconnect reliability with well electronic control. Moreover, NoC offers security control, QoS and power management those bus does not offer, so it has wide application prospect. This dissertation focuses on the research on NoC low power coding, application mapping and clock distributing problem. The major contents are as follows in general:1) Bus and NoC low power codingIn IC design, power becomes one of the most important design objectives.For bus architecture, power consumption decrease effectively by reducing turnover rate of bus signals.For traditional bus architecture, a new low power encoding algorithm was introduced. This solution does not change the bus architecture, and maintain the reusability of IP on bus. The result shows, it reduces the power consumption on bus effectively with minor cost. However, this bus coding scheme is ineffective in multiplexed channel used in packet switched networks. A coding scheme for NoC named SILIENT, and other low power methods for physical layer are also introduced.2) Low power NoC mapping The mapping problem for NoC is to decide how to topologically place the selected set of cores onto the tiles of the network under some constraints.Mapping determines which core connects to which router in the network, thus it greatly impacts both the cost and performance.A low communication power mapping solution was proposed, which is based-on genetic algorithm and subject to latency constraint. It encodes the chromosome as an array of integers, and uses irregular crossover and mutation operations. The results showed that, the proposed solution could effectively reduce the communication power. 3) Multiple-objective NoC mapping In practice, the design objectives of NoC should be considered variously. The scaling of MOS transistors increases the power density, which causes the temperature in high performance chip rise dramatically. If the IPs with high power consumption placed close with each other, it may create the hot-spots region. The hotspot not only has significant impacts on performance, but also leakage power consumption.A power-aware and thermal-aware NoC mapping solution under latency constraint was proposed, which is based on NSGA-â…¡genetic algorithm. The results showed that, the proposed solution could effectively reduce the peak temperature of the chip with minor power addition, compared with single-objective solution.4) GALS clock distributing method NoC integrates numerous blocks with different clock frequencies, facing the difficulties in global-clock tree synthesis and timing validation. GALS (Globally asynchronous, locally synchronous) architecture is a promising solution for NoC clock distributing, it could effectively reduce the clock tree power consumption. However, traditional implementations of asynchronous wrapper for GALS require custom designed circuits, which are not feasible for verification and IP merging. A new FIFO-based asynchronous wrapper was proposed, which implemented using only standard cell and optimized in a standard digital ASIC flow. It achieves high throughput by this wrapper, which needs only two transitions per symbol.The results showed that this wrapper can provide great improvement in throughput and latency.