Error Control Scheme For High Performance Network-on-Chip Routing

Network-on-Chip(NoC) is a hot-spot in research field and is considered as a reasonable solution for integrating plenty of IPs on a single chip. A reliable communication through connection wires is a must for the proper function of the whole chip. But as the rapid shrinking of the technology, crosstalk becomes one of the main noise sources of affecting signal integrity. In order to guarantee a reliable interconnection communication, as well as a high throughput, this paper presents a whole set of reliable transmission scheme for network-on-chip, including an error correcting code, an asynchronous router, 4-phase dual-rail protocol and 4x4 mesh NoC arch. The self-correct ability of our code can reach as high as 10-bit by using group hamming codes. Duplication can nearly eliminate crosstalk effects. Simple circuit based on C-element can translate physical data into higher protocol for routing. The asynchronous router, which is low power and qausi-delay-insensitive, is designed. This router is suitable for multi-clock-domain. By employing channel slicing and look ahead pipeline, the router's highest throughput can reach up to 2.3GB/Node/sec. The novel frame format and transmitting rule makes full use of bandwidth. When the packet is small, the speed can be accelerated about 3 times.