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System Structure Of The Noc Performance Evaluation And Communication Components Are Designed

Posted on:2010-05-16Degree:MasterType:Thesis
Country:ChinaCandidate:Z F YangFull Text:PDF
GTID:2208360272994439Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
At present, the technology node of semiconductor has reduced to 50nm and the number of transistors per chip has broken through 1 billion. The advancement of technology makes the accomplishment of complex system on single chip possible. On the other hand, the consumers' demands for powerful and large integrated circuits(IC) are growing and the disadvantage of traditional bus based SoC(System on Chip) appears increasingly. In such background, people used the historical experience of the development of computer systems from stand-alone to networks for reference and try to resolve the problems in present IC design field by the NoC(Networks on Chip) which is based on communication.The researches and applications of NoC are just in the start-up phase now. The scope of the study is abroad. The main contents of NoC study include topology structures, communication protocols, basic component libraries and the implemental theory and tools by EDA. Based on the conclusion of the theoretical system, this paper focuses on the performance evaluation of NoC architecture and the design of communication components of NoC.After analyzing the performance metrics of NoC architecture, the paper introduces the simulation process of the communication in several ordinary topology structures using the network simulation software NS2. The author obtained the delay, throughput and packets loss rate after dealing with the trace file using awk and compared them by the drawing tools xgraph and gnuplot.In addition, the paper presents the design and simulation process of the NoC communication components - resource network interface (RNI) and switch based on the architecture of 2D Mesh topology. The author wrote the register transfer level(RTL) codes in hardware description language(HDL) Verilog for them, designed the test bench and simulated their functions using simulation software Modelsim. The results show that the logical functions of the RNI and switch are right.
Keywords/Search Tags:Networks on Chip (NoC), performance evaluation, communication component, globally asynchronous locally synchronous (GALS)
PDF Full Text Request
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