Study Of Key Technology In Asynchronous Network On Chips

With the fast development of integrated circuits, the feature size of transistor shrinks rapidly. The growing complexity of circuits makes the synchronous design method exhibit limitations and drawbacks on design and manufacture. GALS design method gradually becomes a hot spot in fields of SoC design, which can be regarded as a valuable complement to synchronous design method. Based on synchronous design scheme, it uses asynchronous design method to connect different modules, thus synchronous and asynchronous design can complement each other's advantages. Meanwhile, to solve high design complexity and power consumption as well as delays brought by global clock tree, asynchronous network on chips which are based on GALS working scheme are gradually become hot spot in research field. Advantages such as high modularity, locally clocking and high concurrency make asynchronous NoC inevitably become the next generation on chip interconnection framework. To achieve the final aim of designing an asynchronous NoC, in this thesis, specific researches were made on key modules (router, channel and wrapper et al.), and specific analysis were made on working scheme, handshake protocol and pipeline scheme. The combinations of asynchronous techniques and synchronous techniques are specifically studied. The main studies and contributions of this dissertation are as follows.1. After analysis of pipeline working scheme in conventional asynchronous routers, this thesis proposes a new design proposal to improve the performance of null convention logic asynchronous pipeline. Parallel combinational logic modules in pipelines can work alternately in NULL and DATA modes by using parallel processing 2mode. The complete waiting time of both NULL and DATA signals of combinational logic output in previous stage of NCL asynchronous register is reduced, while the data processing capacity is increased.2. After asynchronous router and the handshake protocols of transmission channel are analyzed, a data transmission protocol converter is proposed. Specific implementations of several asynchronous protocol converters are shown. Single-rail to dual-rail converter can enhance the robustness of data transmission, while single-rail to multi-rail converter not only can enhance the robustness but also can greatly reduce the power consumption. Four-phase to two-phase protocol converter can improve the throughput of transmission channel; while two-phase to four-phase protocol can simplify the design of combinational logics. The proposal of protocol converter can make the design of asynchronous NoC more flexible.3. A deep study was done on transmission channels of asynchronous NoC. Working principle, handshake protocol and transmission characteristic were analyzed. Optimizations under different design constraints were made to the asynchronous transmission channel. Which include area and interconnection lines optimization, throughput and transmission flexibility optimization, as well as speed optimization. And a series of new design scheme were proposed based on these constraints, such as serial transmission converter, self-adaptive bi-directional transmission channel and single-track protocol transmission channel. These provide a series of channel design scheme for network on chips.4. Working scheme of conventional GALS asynchronous wrapper is analyzed, and two kinds of dual-rail asynchronous wrapper are proposed, which contains four-phase and two-phase wrapper. These two wrappers fit for different kinds of transmission channels. A series of new threshold gates were proposed. Simulation results have shown that the new threshold gates can effectively reduce area and static power consumption. The new gates were applied in the asynchronous wrapper, and the static power consumption is reduced a lot. Furthermore, dynamic frequency scaling is used in the wrapper, so synchronous PE can adjust its working frequency to the work load of the network, thus the dynamic power consumption is also decreased.5. Conventional arbiters in network on chips are introduced. A strictly first come first service arbiter is introduced based on the disadvantages of conventional arbiters. A high speed multi-resource arbiter is proposed combining with allocation function, which can effectively reduce the time needed for arbitration and allocation and enhance the performance of the router. At last, according to the request type, a dynamic arbiter supporting QoS is proposed, which can set the grants according to priorities of the requests. Thus the data packet which needs low latency such as interrupt operation can firstly be routed by the router, and the quality of services can be guaranteed.6. A newly quasi-delay insensitive full asynchronous router is proposed to resolve a series of problems brought by clock tree and multi-clock domain interconnections. There are no long interconnection lines among asynchronous routers, so the difficulties of back end can be lessened. Clockless design scheme decreases the dynamic power consumptions, because asynchronous circuits only use handshake signals to control the working rhythm of the circuits. The proposed router uses multi-resources arbiter to resolve large latency of arbitration and allocation. Results have shown that the performance of this router is better than the conventional one and has better robustness, which can meet most of the applications of NoC.