Low-power RTC Chip Design Based On Asynchronous Circuit

Real-time clock(RTC)is a special integrated circuit for tracking time and date with a wide range of applications.It is suitable where high accuracy time and low power are required.At present,most RTC chips use synchronous structure and the dynamic power consumption generated by the clock tree and switching activity limits their lowest power consumption.Therefore,designing the RTC based on asynchronous models is necessary.This thesis proposes an asynchronous RTC architecture based on the Link-joint self-timed model and the four-wire SPI interface,and it has a calendar,timers and asynchronous interrupts.Through the control network composed of asynchronous handshake controllers,the registers in the circuit are controlled by local clocks with the combination of the self-timed control path and the data path.Because of the lack of synthesis tools for asynchronous models and the large area of asynchronous implementations,this thesis proposes a set of circuit implementations of handshake elements,control flow synthesis algorithm and a Link-joint based synthesis tool CLAM which is able to synthesis and optimizes at the multi-level of behaviour definition,logic cone and netlist through BDD algorithm and genetic algorithm,It can effectively reduces the complexity of asynchronous implementation and chip area.Based on the CLAM toolchain and the SMIC 55 nm technology,this design adopts the bottom-up design method,uses LISP language to design the RTL level of the RTC and uses the Synopsys EDA tools to design,verify and analyze the power consumption of the physical design.Through the analysis of the simulation results,compared with the synchronous implementation,the area of this design is reduced by5.8%,and the total power consumption is reduced by 85.08%.