Design Of Software Radio Architecture And Scheduling Algorithm For Reconfigurable SoC

The software defined radio system has a high degree of integration and a good degree of modularity.Its development goal is to adapt to multi-frequency wireless communication scenarios by loading different communication waveforms on a unified hardware platform.In the SDR system,a unified standard and architecture is the key to shielding the heterogeneity of the underlying hardware devices and realizing the smooth switching of communication functions.At present,among the military SDR communication equipment,the software communication architecture of version 4.1released by the US military is the most widely used.Traditional hardware computing devices such as CPU,DSP,FPGA under this architecture are virtualized into logical device components,and componentized hardware resource management is realized through standard interfaces and packaging.At the same time,with the emergence of new computing scenarios such as 5G,cloud computing,and edge computing,the semiconductor process is gradually approaching physical limits,and traditional hardware computing equipment has gradually been unable to meet large-scale computing needs.Xilinx has developed an FPGA with a new computing architecture with smaller reconfiguration granularity and dynamic partial reconfiguration capability.This chip not only integrates DPR FPGA,but also contains the CPU core of ARM architecture.It is a heterogeneous multiprocessor system-on-chip with dynamic partial reconfiguration characteristics,which we call DPR HMPSo C.The new FPGA provides abundant parallel heterogeneous computing resources.However,the existing SCA architecture only supports FPGA coarse-grained resource virtualization,which reduces the flexibility of waveform component deployment and FPGA hardware resource utilization.In order to improve the SDR system's fine-grained resource virtualization and parallel computing capabilities for FPGA resources.Based on the existing SCA standards,this paper designs a software architecture that supports DPR HMPSo C computing devices;at the same time,researches on the software and hardware partitioning and scheduling technology of waveform components for DPR HMPSo C computing devices to further improve the execution efficiency of the components and the resource utilization of hardware.The specific work is as follows:1.Man use XML to design the domain description file software architecture under the SCA standard,so that SCA has the architecture support for the fine-grained resource virtualization of DPR FPGAs.The DPR deployment mechanism of waveform components is proposed,and the mapping relationship between waveform components and DPR FPGA reconstruction sub-regions is established.2.Aiming at the software and hardware partitioning and scheduling problems of the DPR HMPSo C computing platform,we use directed acyclic graph to complete application modeling,and propose a list heuristic software and hardware partitioning and scheduling algorithm based on greedy strategy-e HEFT(expanded Heterogeneous Earliest Finish Time).3.Based on randomly generated DAG and practical application DAG two sets of test benchmark data sets,we conducted algorithm simulation comparison experiments and data analysis.The experimental results show that the e HEFT algorithm performs better than the comparison algorithm in the two performance indicators of the applied scheduling length and the algorithm's solution time.Under constrained conditions,the solution performance is improved by more than 20% on average,and the solution time is greatly shortened.