A Study On Co-scheduling Hardware And Software Based On Dynamic Partial Reconfiguration Technique

When general processor and ASIC (Application Specific Integrated Circuit) have the bottle-neck in application fields, Reconfiguration computing as a novel two-dimensional space-time computing model, which have the flexibility and high performance, can play a huge role in the application fields where the traditional calculation can’t satisfied. Especially Dynamic Partial Reconfigurable (DPR) technique can change the partial hardware logic function in FPGAs (Field-Programmable Gate Arrays) at runtime, realize the multiplexing of hardware logic resources.Dynamic Partial Reconfiguration System on Programmable Chip (DPR-SOPC) integrated software and hardware on single chip. Operate System on chip can flexibility schedule software and hardware for software/hardware co-scheduling. Through combining the advantages of software and hardware, balance the system computing resources and enhance the whole performance efficiently. This paper mainly completes the following several aspects of works:(1)This paper gives a brief review of the related concepts and evolving history about reconfigurable computing. To take the Xilinx Virtex series FPGA for an example, introducing FPGA inside structure, program method and configuration method.(2)Through comparison various different reconfigurable technologies, this paper analyzes the advantages and disadvantages of three technologies. Make sure the Early Access Partial reconfiguration (EAPR) technology to design the DPR-SOPC platform. Making a thorough study in one-dimensional and two-dimensional reconfigurable, analyze their difference.(3)This paper presents a new co-scheduling software and hardware platform DPR-SOPC based on dynamic partial reconfigurable technique, and a detailed description of overall design thoughts and framework. Using Xilinx Virtex FPGA as the development platform, describe the process of DPR-SOPC hardware environment design flow and how to scheduling hardware task.(4) μC/OS-Ⅱ Operating system is transplanted on PowerPc405. Analysis different attributes between software and hardware, according to their own features, design the software and hardware task state transition model, put forward the basic principle of the task scheduling. Introducing the soft/hard compound task in balance the processor load and reconfigurable region load, and improve the system efficiency.(5)This paper presents a new fault tolerant and self-repairing strategy based on DPR-SOPC. The fault tolerance strategy mainly realizes the protection of critical task in the reconfigurable region. DPR technique is used to repair the error induced by SEUs, through reprogramming the reconfigurable region. The presented strategy adopt co-scheduling software and hardware, flexibility realizing variety fault tolerant methods, with more extensive application environment, balance system reliability and the relationship between the performance.