Research And Design Of Energy Efficient Pipeline Adc

Recognizing energy consumption an important part in the perspective of the climate change and global warming, reducing the energy dissipation becomes consensus in the circuits and system society. Since analog-to-digital converters (ADCs) are essential building blocks in virtually all systems, the importance of research on energy-efficient ADCs is obvious and validated by the development history track of wireless communications and consumer electronics during the last decade. Besides consuming less power by themselves as blocks or modules in the application system (system-on-chip or system-on-package), energy-efficient ADCs are increasing important for smart system architecture partitioning, which may result in impressing energy saving, cost-effective fabrication, or development period shortening, of the whole application system.One emphasis of the thesis in on digital calibration algorithms with enhanced robustness and improved convergence speed to correct the analog circuit imper-fections and to enable the high linearity pipelined ADCs. A review of calibration techniques, especially those with fast converging speed, is presented. A simple foreground/background hybrid calibration algorithm, naming as time-spreading digital calibration, to calibrate the errors due to finite gain and capacitor mis-match in multi-bit/stage pipelined ADCs, is developed with short convergence time.Another emphasis of this thesis is on a number of circuit and architecture techniques for low power pipelined ADCs, to eliminate or minimize the noise and nonlinearity errors, which are difficult or complex to correct with digital algorithms. A common-mode-sensing-and-input interchanging (CSII) technique is proposed for OTA-sharing architecture to eliminate potential memory effect-s. The settling constraints of multi-bit multiplying-digital-to-analog-converter (MDAC) front-end in high resolution ADCs and techniques to improve the set-tling speed are discussed. A novel architecture to improve the settling efficiency of high linearity multi-bit MDAC is also included in this research, referred as workload-balanced MDAC (WB-MDAC).Research on and development of the programmable energy-efficient ADCs is also within the scope of this thesis. A1.2V12bit5～45MS/s speed and pow-er scalable pipelined ADC is designed and demonstrated in a0.13μm CMOS technology. The designed programmable ADC achieves good performance and low power consumption, comparable with state-of-the art power scalable ADCs, which shows the effectiveness of some of the proposed circuit techniques:(1) OTA-sharing and improved SHA-free topology to minimize the power consumption,(2) adjustable current bias of OTAs, comparators and reference buffers to maintain a good power/speed ratio,(3) CM-sensing-and-input interchanging technique to cancel memory effects in an OTA-sharing architecture. The measured signal-to-distortion-and-noise ratio (SNDR) is in range of62.5dB to69.2dB, and the peak spurious free dynamic range (SFDR) is80.7dB for all speed options, while the figure-of-merit (FoM) is in the range of0.26-049pJ/conversion. The core area of the die is1.5mm2.The power-linearity tradeoff in pipelined ADCs is very significant in or-thogonal frequency division multiplexing (OFDM) communication systems. In this dissertation, a14-bit50-MS/s digital calibrated pipelined ADC with WB-MDACs is also presented. Nonlinear errors due to finite gain and capacitor mismatch are addressed by using a digital background calibration algorithm, which is implemented off-line and operates in MATLAB software, to minimize the power overhead. The analog core of the ADC, modified to inject dither in first three stages for calibration, is realized in0.13μm1P8M CMOS technology, and occupies an active area of1.3mm2. The measured SNDR/SFDR were im-proved from58.6/66.5dB to64.4/81.9dB with the input frequency of4.7MHz, by enabling the calibration. It dissipates76mW from a1.2-V supply, excluding the internal reference buffer and the digital calibration logic. In case that ENOB in term of SFDR, instead of ENOB in term of SNDR, is used to calculate the power efficiency, its FoM2might be0.19pJ/conversion.