The Design Of 10-Bit SAR ADC

The ADC10A is a 10-bit, successive approximation (SAR) analog-to-digital converter (ADC) which is fabricated in CSMC 0.5μm double poly triple metal mixed-signal CMOS process which this paper designed. This integrated circuit (IC) was attended CSMC MPW tape out in Sep 15,2005 when the design was finished at Beijing MX-Device.The ADC10A is a mixed signal system which contained analog signal and digital signal. This paper uses top to bottom design method, the design target that puts forward at first which includes 10-bit resolution with 500ksps throughput rate, low power consuming when the chip working in a 3.3V signal power supply that is 4.75mW and the bandwidth is higher than 8MHz. Then set up the layout of the chip. The chip layout structure is divided into adc10a_core and i/o_pad. Inside the core there are three important models, such as digital-to-analog converter (DAC), voltage comparator and some other digital logic units. The circuit of DAC is a type of charge redistribute that consisted of resistance array and capacitance array. Each conversion switch is controlled by CMOS transfer gates. The voltage comparator is consist of three step folded cascade operational amplifiers and a sensible amplifiers. The digital logic units are generates various control signals that making internal and each module be in conjunction with a work.The circuit makes some simulations when the design were finished. All simulation results were satisfy (mostly better than) the design target.The layout design is based on the modules of ADC10A, then passed DRC and LVS when the design were completed, get the netlist to make post simulation which includes parasitic parameters, the simulation results were satisfy (mostly better than) the design target.All works were compeleted in PC and the SUN working station, some software are used such as the Workview office system, the L-edit and Hspcie during the design. Then applied Dracula checks the DRC and LVS of the layout, and combine Composer and Virtuoso to revise further to the schematic and the layout which embed in Cadence system. In the design there are some useful libraries such as the fabrication library "h05mixddst02v13.lib", the 0.5μm devicesand standard cell library which were supplied by MX-Device and the DRC rule "csmcO5.drc" and LVS rule "csmcO5.1vs".The chip of this thesis design has successfully attended MPW tape out in CSMC, now in testing.