Research On Key Techniques Of NoC-based Many-Core Testing

Many-core chips are designed for high efficiency parallel computing. Hundreds to thousands of cores, which belong to different kinds of cores, are integrated in future many-core chips by on-chip network. It is shown in the ITRS2008 (International Technology Roadmap for Semiconductors) that the amount of signal pads is fixed with the increasing number of on-chip transistors. Accordingly, the many-core chips testing time still increase even if parallel testing methods are used. It would increase testing cost. It is necessary to achieve new efficient parallel testing techniques to solve the important problem of long testing time.It is well known that power dissipation during test mode can be significantly higher than that during functional mode. When the heat generated by the cores parallel testing in a same area could not dissipate in time, it may be cause HotSpot. HotSpot would increase leakage power of CUT (Circuit Under Test), and cause much crosstalk noise. It also could bring missdetections and undetections, and even cause physical damage to transistors. So, the thermal and the temperature in test should be under control.This thesis is a research on parallel testing techniques of many-core chips. Multicast Paths Testing Method for NoC-based many-core and multicast-support SoC is presented to reduce test time. Thermal-aware parallel multicasting testing method is proposed to avoid HotSpot in parallel testing. The main work and innovation are depicted as follows:(1) A low-power scan structure named PowerSluice is proposed to minimize power consumption in scan test of a signal core, which is based on a scan chain modification technique. In this method, an obstructive logic circuit is inserted into the scan chain to reduce the dynamic power and a control unit is used to decrease the leakage power in the shift stage and the genetic algorithm is used to get proper values of control signals. Some experiments are made and the results indicated that this method can effectively reduce power consumption in scan test and maintain the test fault coverage. When the average fanout number is more than 1.5, PowerSluice has the least area among the existing gating techniques. (2) This thesis presents an efficient testing method called Multicast Paths Testing Method for NoC-based many-core and multicast-support chips to reduce test time. Multicast communication is used to realize test data transmission for homogenous cores. On-chip Comparators are used to avoid the traffic jam caused by the test response transferring in the on-chip network. The parallelism of multicast paths is supported by Virtual Channels. It would further reduce test time. Experimental results show that MPTM could reduce test time by over 85% for large scale many-core chips compared with serial testing, and have a better effect with growing NoC size.(3) Long testing time and high power density have become critical problems during test of today's many-core chips. These two facts may result in partial overheating. In this thesis, we propose a thermal-aware parallel multicasting testing method. We analyses HotSpot caused by parallel multicasting test in many-core chips. Algorithms are presented to avoid HotSpots in the generation of multicasting test access paths for each kind of identical cores. Then, our method gives an optimized solution of selecting candidate multicasting test access paths which can coexist with thermal constraint, so that the parallel of multicasting test access paths can be realized. Experiment results show that the temperature on chip can be controlled and HotSpots can be eliminated, efficiently. With growing NoC size, the proportion of test scheduling-induced test cost could be further decreased.