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Design And Research Of Discrete Cosine Transform IP Croe

Posted on:2009-12-18Degree:MasterType:Thesis
Country:ChinaCandidate:M JiangFull Text:PDF
GTID:2178360245973339Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
Discrete Cosine Transform(DCT)and Inverse Discrete Cosine Transform(IDCT) have been widely used in coding and decoding of image processing recently.Up to now,it is adopted by many international standard groups including JPEG,MPEG1, MPEG2,MPEG4 and H.24x etc.It is difficult to make a real-time implementation of it by software method because it takes too many CPU cycles,in contrast we use hardware implementation to satisfy the processing rate requirement.This thesis has been mainly taking account of hardware implementation of 8×8 2D DCT IP core for application in image processing.Firstly,the theory and advantages of using Discrete Cosine Transform and Inverse Discrete Cosine Transform in images compression is presented.We portrayed the process of using DCT/IDCT in image compression.Then we made a vivid discussion among several fast DCT algorithms and gave detailed introduction of Loeffler's fast DCT algorithm which was discussed in this paper.The IP core use the Row Column decomposition Method(RCM)to decompose the two dimensional DCT into one dimensional DCT.When calculating the 1D DCT/IDCT,we made some improvements in Loeffler's fast DCT algorithm according to the characteristics of image compression.After rearranging and simplifying the calculation cycles,we got a shorter critical path and thus speed up the pipelining.The multiplication in the DCT algorithm adopts fixed coefficient.Based on the precision requirement of the DCT finite length in CCITT,a simulation of finite length is carried out.A Ping-pang process of storage is used to achieve the transpose operation of the temporary data.A top-down design method is proposed to implement the IP of discrete cosine transformation.First of all,the system-level theme of the design is introduced, followed by a description in behavior-level language using Verilog HDL.Next,the design is completed on the platform of Xilinx ISE and checked by Xilinx VirtexⅡ. The chip is implemented in TSMC 0.25um process with a total area of 1.2mm~2.The measurement result shows that the maximum operating frequency can be up to 108.7MHz,and power consumption is 73.64mW totally.
Keywords/Search Tags:Image compression, Discrete Cosine Transform (DCT), Field Programmable Gate Array (FPGA), Register Transfer Level (RTL)
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