Design And Optimization Of Reconfigurable Array For DCT And IDCT

Discrete Cosine Transform(DCT)and Inverse Discrete Cosine Transform(IDCT)are widely used in the field of media processing and adopted by many international standards,including image coding standard JPEG,video coding standard H.26 x and MPEG-x series,etc.DCT and IDCT have a large amount of computational data,and have high requirements on the computing power and real-time performance of the processing system.The coarse-grained reconfigurable platform is an ideal platform for implementing DCT/IDCT operations,which combines the flexibility of a general-purpose processor with the high efficiency of a dedicated integrated circuit.This thesis will design and optimize the key components of the reconfigurable array framework,so as to improve the computational speed of DCT and IDCT on the reconfigurable array.Firstly,by analyzing the basic operation of DCT/IDCT and the statistical characteristics of data stream,and the circuit structure of the processing unit is designed,in which the multiply-add unit and the data output unit are optimized.At the same time,the corresponding configuration information format is defined to support manual mapping of different algorithms.According to the characteristics of data compaction,computational intensiveness and small data correlation of computationally intensive algorithms,by analyzing the advantages and disadvantages of different storage structures,the distributed data RAM structure and the configuration RAM structure supporting SIMD computing mode are designed to improve the loading efficiency of data and configuration information.Based on the row-column decomposition method and the optimized design of the reconfigurable array structure,the mapping scheme of two-dimensional DCT/IDCT is determined,and one-dimensional DCT/IDCT mapping is performed on the rows and columns respectively,and a fast one-dimensional DCT/IDCT algorithm matching the existing architecture is selected,so as to achieve faster computing speed.By analyzing the data flow characteristics of the fast algorithm,the interconnection structure of the array is optimized,on the basis of satisfying the computational intensive algorithm mapping requirements,the processing unit utilization and computational speed are further improved when mapping DCT and IDCT.For the interconnection structure optimized for DCT and IDCT,the processing unit utilization rate is the same as the full interconnection structure,reaching 71.4%.Compared with the Mesh interconnection structure,the processing unit utilization rate is improved by 20.4%.The simulation results of the reconfigurable array show that the calculation accuracy of DCT and IDCT meets the requirements of IEEE1180-1990 standard.The 8×8 two-dimensional DCT and IDCT operations both require 16 clock cycles,and the computing speed is increased by 55.6%,compared to the same type of reconfigurable processor SmartCell.