Implementation Of Variable Length Decoder,Inverse Quantization And Inverse Discrete Cosine Transform In MPEG-2 With FPGA

Along with the development of digital television, people are paying more attention to the MPEG-2 audio and video coder, the MPEG-2 audio and video decoder. The programmable logical component's FPGA and CPLD substitute ASICand DSP increasingly and are being used to realize the digital signal processing algorithm. The signal processing system of FPGA/CPLD have many merits: such as the very high timeliness, may inserting other systems, conveniently realizing integration, function expansion and so on. This article uses FPGA to realize the MPEG-2 video decoder's three function modules, VLD (Variable Length Decoder), IQ(Inverse Quantization) and IDCT(Invese Discrete Cosine Transform).Based on the design of the high-speed multiplier circuit, this article ends up realizing the IQ and IDCT of MPEG-2 video decoder with FPGA. Through analying and designing the FSM, this article finally appling it to realize VLD with FPGA.Through researching the algorithm of high speed multiplier circuit, this article proposes a kind of hardware multiplier circuit which is based on 4 Booth algorithm, in order to enhance the operating speed of the hardware multiplier circuit. This article...