Study On Key Technology Of Integrated CMOS Camera

At present optical imaging, image transmission and data recorder such discrete part made of a photoelectric measuring system largily. It is large in size and weight of heavy and low reliability.So considering developing optical imaging, data storage and transmission as a whole is put forward to enhance the flexibility, management and programming ability of the system. The key point of this paper is to develop a high-performance integrated camera with imaging, storage and transmission function which has high frame rate, large capacity, low error rate and can manage different task according to the needs.In CMOS imaging subsystem, based on analysis performance and technical features of Cypress's LUPA-300, CMOS imaging subsystem is developed, and a two-point real-time correction algorithm is adopted to solve the pattern noise of the sensor. Experiment shows it can take about 4310.34fps at a resolution of 128×128 and 253.94fps at a full resolution of 640×480.Image recording subsystem contains the data storage and transmission.Considering that single NAND Flash has low speed, small capacity and existing invalid block, the reliability storage solutions of high speed and high capacity image recording is proposed. The structure and characteristics of NAND Flash is analyzed .Then by separating written invalid block from non written invalid block, the classified data matching and detection mechanism based on CAM is proposed to raise invalid block information matching speed. The SRAM array backup and dual pipelining mechanism based on dual bus structure is proposed which adopting SRAM array of backup data to prevent data writing error, when invalid block is occurring in multiple pipelining grade during writing and dual pipelining mechanism to prevent pipelineing interrupt and guarantee high speed. The system has different resolution in windowed mode, through a parameterized RS codec strategy with FPGA is proposed with storage and transmission program based on dual bus structure.So the problem of the high recording speed with the invalid block of NAND flash and data inverse is settled, the reliability of the system is improved.In integrated CMOS camera, based on dual bus structure with SRAM array, single mode and composite mode is proposed, for example, synchronous reading writing mode and synchronous writing erasing mode. According to the integrity grade of the data request,the speed mode and non - speed mode is presented which increases flexibility of the system.File index information which is stored in non-volatile FRAM is isolated from flash memory. DSP is used to manage the whole task of file information. The information in FRAM is updated after the writing event and before erasing to protect suddenly power off and ensure reliability of the camera. The whole block of the flash array is partitioned to several district, each which has usage variables to manage the valid block cluster which extends the life of the camera.Then the priority of operation and bus arbitration threshold strategies are studied to prevent bus conflict. At last the protocol among integrated camera with master controller and various subsystems interior the camera is studied,the content of the FRAM is regularized, and the operation manage strategies for various task integrated camera is proposed.The experiment show the storage capacity of CMOS integrated camera is 254.7GB.The frame rate is up to 253.94fps at a full resolution of 640×480 at which the largest error-correcting capability if up to 72 bytes per page.In high speed mode, the speed is more than 400MBps.In non -speed mode, the imaging speed is more than 100MBps.The consumption of the camera system is less than 10W.