Nand Flash Fast Bch Code Decoding Algorithm And Will Achieve

Parity check and CRC are usually used in modern digital communication. A traditional checking method ECC is popular for data check of NAND Flash using SLC technique. In recent years MLC technique is developed in producing NAND Flash memory which may generate more then 2bit error in one page. BCH checking should be used in MLC NAND flash memory because of its check and correct capability. In that case BCH algorithms and its optimizing method are rapidly developed by electronic engineers.BCH code is a circulatory linearity code which can correct more than 2bit errors. The thesis introduces the principle of binary BCH, and then generalizes the theory of BCH coding and decoding for detail. The main content in the paper is as follows:Firstly, introduce background and academic basis of BCH code and give some introduction of NAND Flash in brief. Secondly, research BCH code through coding methodology of serial / parallel and algebraic/non-algebraic conception. Thirdly, BCH (4200, 4096) code syndrome coding and decoding are implemented in SOC and simulation result is obtained from part three and four of the paper. Finally, there is description of chip design in SOC . Also, the testing result of the chip is included in the last part of the paper.Based on TSMC 65nm technology , Candace NC-sim for RTL simulation is used and false model with data communication error and correcting is obtained . In the synthesize phase, Synopsys DC is used. There are about 30,000 gates for NAND Flash Controller and the work frequency is 125MHz in the synthesis report.Chip ATPG (Automatic test pattern generation) test is passed both for controller and whole system. Data in the memory are read and wrote correctly. The chip works well under the high/low temperature and high/low voltage. The performance of the chip is same as the design spec.