Study Of Reliability On Partial Block Base On 3D NAND Flash

The invention of 3D NAND Flash has made up the huge gap between conventional memory and DRAM in speed,which improves the efficiency of computer system.Due to development of 3D stacking technology and decreasing process cost,3D NAND Flash has been considered to be a very promising candidate.One of the most important factors in the product development process is reliability,because 3D NAND Flash uses charge to store data.Most of the research on the reliability of 3D NAND Flash focuses on fully programmed blocks,but the actual controller behaviors are mixed with complex reads and writes,which involves the operations on partially programmed blocks.However,the physical structure of partially programmed blocks often leads to reliability risks.This article studies the reliability of the partially programmed blocks through the root cause of the 3D NAND Flash error.The risk of edge WL in partially programmed blocks is found,and high raw bit error rate occur when reading with the V_default or experiencing long time data retention.At the same time,three unreliable operations on partially programmed blocks are found:1)performing frequently single page read operations on the edge WL;2)performing a program operation on an un-programmed WL which after long time data retention;3)performing erase operations on partially programmed blocks.In addition,the programming data pattern,active GC activation method,and erase execution part are optimized to handle these issues and achieve the improvement of the reliability of the chip.