Font Size: a A A

The Design Of High Speed And Reliable Storage Based On Nand Flash Array

Posted on:2018-08-02Degree:MasterType:Thesis
Country:ChinaCandidate:L B JiaFull Text:PDF
GTID:2348330515483702Subject:Instrument Science and Technology
Abstract/Summary:PDF Full Text Request
In the acquisition of image data,storage system needs to meet the requirement of high-speed image data storage.Aiming at image information processor performance test requirements,develops a high-speed image data parallel storage system.In order to realize the large capacity,high speed,high reliability,low power storage requirements,this paper is devoted to research a kind of high speed image data storage method,and the high reliability and low power consumption involved in high-speed storage.First of all,in order to realize the continuous storage of 200 MB/s speed,drawing lessons from the thinking of pipeline and parallel extensions,designs a structure for 5 x 8 Flash storage arrays,the pipeline design within and between channels with state machine,through a parallel work mode in the form of the double pipelines,give full play to each of Flash storage performance to achieve the sustained and rapid storage of image data.Secondly,in terms of reliability,aiming at invalid block management problem of Flash arrays,puts forward two kinds of invalid block management scheme,and analyzes the advantages and disadvantages of two kinds of invalid block management scheme,choose the invalid block management scheme based on composite block concept;At the same time,in order to solve the sudden invalid block influence on high-speed storage,lag to rewrite is designed.In addition,in view of the Flash data error caused by single bit flip chip,hamming code error correction scheme of the double cache alternation is put forward,and the solution does not affect the data read speed,effectively avoid the generation of single bit error of the Flash.Finally,in order to reduce the power consumption of the FPGA and the chip fever,a low power optimization method of program design is proposed,using this method can greatly reduce the use of the internal logic and routing resource,so as to reduce the dynamic power consumption,improving the reliability program runing of the FPGA.Through the performance test of the technology and overall device,analyze and calculate the test data,the design of the Flash array can reach 200 MB/s rate of data storage.A large number of experiment proves that the rate and capacity of the storage system meet the design index,and the work is stable and reliable.
Keywords/Search Tags:image data, Flash arrays, pipeline, invalid block
PDF Full Text Request
Related items