| With the rapid development of communication,cloud computing and big data,the issue of information security attracts more and more attention.Random numbers which are used as keys or public keys,initialization vectors,and padding values play a critical role in modern security systems.Since the pseudo-random numbers is generated by the deterministic algorithm,it has certain predictability and will bring hidden dangers to applications in security systems.Because of the demand for high-reliability information encryption,pseudo-random numbers have been unable to meet high-quality requirements,so the development of true random numbers has attracted more and more attention.Due to the demand for lightweight security devices such as the Internet of Things,true random number generators require not only low resource overhead,but also high throughput.In addition,FPGA has been widely used because of its impressive speed at lower cost and faster design cysles.For hardware implementations of secure encryption,FPGA is an ideal experimental platform.More and more encryption systems implement high quality true random number generator on FPGAs.In this work,a novel low-cost,high-efficiency true random number generator based on the ring oscillator is implemented on FPGAs.Forming a tapped delay line by utilizing the fast carry logic on FPGAs,we have improved the efficiency of the entropy extraction from the jitter of single transition event rather than multiple jitter accumulation like most RO-based TRNGs.The proposed structure has been validated on the Xilinx Virtex-6 FPGA development board,using only 25 slices and achieving 100 Mbps throughput.In order to verify the stability of the structure of this paper,we conducted a PVT test.The experimental data show that the proposed structure has good robustness under different voltages(0.9V-1.1V)and temperature(0°C-80°C),and is suitable for FPGA development platform for different processes.The generated true random numbers can pass all the NIST randomness test. |
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