Research On Security Strategies For Data Remanence In Static Random Access Memory

Static Random Access Memory (SRAM) is a kind of non-refreshed semiconductor memories. Each memory location in SRAM can be read or written in a random order. As it has the characteristic of high operation speed and low power consumption, SRAM is widely used in many high performance microprocessor and various consumer electronic products. It is commonly believed that SRAM belongs to the volatile semiconductor memory. The information represented by data in such memory will disappeared immediately after the power supply is removed. However, in recent years, the fact of data remanence in powered-off SRAM has been continuously reported and researched. Moreover, some professional methods are developed to recover the remained data or read it out. In practical applications, the security of SRAM and its applied system has been greatly threatened by it. In this thesis, the design and implementation of security strategies for data remanence in SRAM are comprehensively and thoroughly investigated.To begin with, sorts of typical physical attacks to SRAM are discussed, and the mechanism of them is studied respectively. Based on the theory of semiconductor physics and devices and the experimental data, the physical explanation of data remanence in SRAM is presented, which is the theory basis of designing security strategies.Secondly, most of efforts are devoted to the research and design of key technologies including the system architectures of SRAM employing zerosition and rewrite secure methods, the on-chip system of energy acquisition, storage, and conversion, and the low-voltage high power efficiency charge pump elevator. The powered-off SRAM utilizing different security strategy to data remanence needs different system architecture and function blocks. So the structures of various security SRAMs and its secure circuits including low power consumption powered-off detector, low loss power supply selector, zerosition array and rewrite array are respectively researched and designed.To provide the energy to accomplish secure operations in powered-off SRAM, a fully integrated power supply system to realize the on-chip acquisition, storage, and conversion of energy is proposed. The system adopts capacitor to reserve charge and accumulate energy, which avoids the electromagnetic interference and reduces the parasitic resistance comparing with the method of using inductor. The system utilizes charge pump elevator to enhance the voltage of storage capacitor and effectively increase the reserved energy. Meanwhile, charge pump elevator in powered-off state is reversely cut off to prevent energy leakage to ground. Moreover, the system also integrates linear regulator which is quite applicable in on-chip power supply system. Founded on studying the electrical characteristic of it in quasi powered-off state, the linear regulator realizes an efficient energy transfer from storage capacitor to secure circuits. Furthermore, using Huahong-NEC (HHNEC) 0.25μm CMOS technology, the optimized design method of system parameters for on-chip power supply is presented by considering different SRAM architectures employing different security strategies.To avoid attackers to dissemble the secure circuits, the design technologies of low-voltage high power efficiency fully integrated charge pump elevator are studied. The model between power efficiency and clock overlapping for charge pump elevator is established, and the optimized clock control strategy to achieve the highest power efficiency is proposed. For four phase Dickson charge pump, the range of optimized clock overlapping is 3%～6% of one period of clock signals, which increases 8% of power efficiency at most. Utilizing low cost P-sub N-well process and compound device, we propose a novel high power efficiency all-PMOS charge pump which has the advantages of four phase Dickson charge pump and Doubler charge pump.Finally, implemented by HHNEC 0.25μm 1P5M CMOS technology, two SRAMs employing proposed security strategies are realized. Based on the principle of physical attack using low temperature frozen technology to data remanence, the verification method is presented. Two SRAMs employing different security strategies show data remanence is successfully eliminated or altered, which means the two security strategies can resist physical attack to data remanence. Comparing with the conventional SRAM, the operation power consumption of each SRAM is only increased by 4% or 5% respectively. Moreover, write and read operations of two SRAMs are the same as the conventional one.