The High Voltage Generation System Design In Nano-Crystal Memory

In the past half century, Flash memory has become one of the fastest growing kinds with its high integration and high reliability characteristics. Based on these properties, Nano-Crystal Memory (NCM) further improves the storage density. And owing to its good compatibility with CMOS process, NCM shows a great scientific and industrial value. On the other hand, decreasing the supply voltage, so as to achieve low power consumption on chip level, has become an important direction in VLSI. However, in order to realize the correct operations in NCM, high voltage is necessary to obtain high electric field. So, the internal high voltage generation system is critical to the chip performance in NCM.The achievements of this paper are part of the project– an 8Mbits low-power high-speed embedded NCM chip system in the Institute of Microelectronics, Chinese Academy of Sciences. The process is based on GSMC 0.13μm 2P3M NCM process and standard 0.13μm CMOS embedded flash process.This paper first introduces the operation principle of the NCM. According to its operation methods, the architecture and functions of the high voltage system in the whole chip are proposed, and then the high voltage generation circuits are detailed described and analyzed. The chip includes four charge pump systems to supply the positive and negative high voltages for memory operations. A charge pump system mainly consists of oscillator, four phase clocks generation circuit, core charge pump circuit and regulator. Through the comparison of the performance of the commonly used charge pump topologies, this paper selects a most efficient one to implement. And based on which, the detailed design process of the positive and negative charge pumps are presented. Moreover, the design of the clock generation circuits and the regulator is also introduced. The simulation results indicates, the performance of all the charge pump systems meets chip requirements well in the worst working case.Since all the high DC voltages are directly supplied by charge pumps, the power efficiency of which becomes significant to chip power consumption. Owing to this, this paper presents an efficient, fast and accurate charge pump efficiency optimization methodology based on statistics. It shows that, under a compact experiment scheme, this technique only has a 1.56% error.Finally, chip layout, high voltage system layout and the layout of every single module are proposed.