Design Of Power Management Modules Of Printer Consumable Chip With Low Power Consumption

Under the single bus communication protocol,only one line is used for communication between the master and the slave.This line should act as both the signal line and the power line.In the communication state,this line can not always be high level,and it will be switched to zero potential in some time period.In this time period,it can not supply charge to the internal circuits of the chip,only the charge stored on the power capacitor can supply charge to the circuits.In this way,for the internal circuit,the input-power voltage supplied will decrease.The longer time for which the signal line keeps in pulling-down state,and the greater the power consumption of the internal circuit is,the more voltage of the input power supplied will drop.When the power supply voltage is too small,the performance of the driven circuits will be poor,some of them can even not work,which makes the internal circuit modules need to adopt low-voltage and low-power design.Aiming at the printer consumable chip under the single bus communication protocol,this dissertation designs three modules related to power management: Vref,LDO without large capacitance and high voltage charge Pump for Flash or EEPROM to erase and write,under the input voltage of 2V?3.3V,owning low power consumption,which has much value in practice.In the design of voltage reference source,the band-gap reference structure of current modular sum is selected,whose input voltage limit can be less than 1.3V;the single-stage operational amplifier without bias circuit is used in the operational amplifier circuit,which decrease the number of branches and reduces power consumption of the circuit.LDO adopts PMOS power transistor architecture,which ensures that the circuit can achieve 1.5V stable output at a low input voltage of 2V;similarly,the operational amplifier adopts a single-stage operational amplifier without bias circuit,and using a simple Miller capacitance compensation method to achieve loop stability,which reduce the total number of branches of the circuit and reduce the power consumption of the circuit.Pump adopts the optimized CTS structure based on Dickson charge pump architecture,which eliminates the threshold voltage loss of each MOS stage and improves the boost efficiency;the charge pump stage adopts the lowest power consumption stage design under input voltage of 2V,and uses the control of the opening and closing of the clock drive circuit to stabilize the voltage,which can reduce the power consumption of the clock drive circuit and realizes the low-voltage and low-power design.The circuit is simulated by Cadence Spectrum simulator,Based on HHgrace 0.13 um 3.3V Flash process model(tt).The temperature drift coefficient of the voltage reference source is 10ppm/?,the rejection ratio of the low-frequency power source is 51.5d B,and the static power current consumption is 7.5?A.Compared with the traditional structure,the static power consumption can be reduced by about 28%.The output voltage of LDO is 1.5V,the rejection ratio of the low-frequency power source is 83 d B,and the load current changes 5m A within 10?S,the transient response keeps well,and the static power current consumption is only 11?A,which is reduced by about 21% compared with the traditional structure.The output voltage of charge pump is 18 V with the load current being 2u A,at the lowest input voltage of 2V,the establishment time is 57?S and the ripple voltage is less than 400 m V.