Design Of Charge Pump System For Floating Gate Memory

Due to the feature of non-volatility, ability to electrical erase and program and the comparatively low cost, the floating gate memories have a wide application recently. The current floating gate memory devices include EEPROM, NAND Flash and NOR Flash, all of which have an operation voltage of less than 5 V. However, these devices need higher voltage to erase and program the memory cells. Therefore, an on-chip high voltage generating circuit is essential to accomplish erasing and programming operations.This passage research and analysis on the high voltage generating circuits such as the voltage transformer, Cockcroft-Walton circuit, charge pump circuit and Boost converter, and derive that the charge pump circuit is the most suitable circuit for the high voltage generator in floating gate memory based on the feature of the process of the integrate circuit. This passage get a further analyze of the basic principle of charge pump circuit, statistic characteristics and dynamic characteristics based on the Dickson charge pump circuit. The passage also generalizes the theoretical derivation of the basic parameter of the charge pump circuit including output voltage, rise time and so forth. In addition, several different method of overcoming the problem of threshold voltage drop and the effect of bulk biased in Dickson charge pump circuit are generalized, as a result, a charge pump using NCP-2 structure is chosen in this design.In order to solve the problem of determining the number of stages of the charge pump mostly by experience but not considering the efficiency in the conventional charge pump circuit, a design technique based on the power efficiency optimization is proposed and an 8 stages NCP-2 charge pump is designed. The charge pump circuit need a regulation circuit to hold the voltage as a constant, because the charge pump system need to provide a stable output voltage under the conditions with different load. After analyzing several strategies of regulation, a regulating method of controlling the clock is adopt in this design, moreover, the essential circuit in the regulator including voltage divider, bandgap reference circuit and comparator are designed.Eventually, the SMIC 0.35μm 2P3M EEPROM process is adopted to implement this design. The output voltage of the circuit designed is 16 V, and the area of layout is 79040 square micrometers. The test result indicates that the charge pump operates normally and that all performances meet the design requirement.