Design Of The Charge Pump System In The Flash Memory

The lower power consumption is the trend in the VLSI circuits. Lowering the voltage supply is an effective way to reduce the power. However the gate oxide thickness can't be less than 8nm in order to maintain the 10 years'data retention in the nonvolatile memory. However a high electric field must be forced at the gate oxide in order to implement the erasing and programming operation. So the high voltage (generally larger than power supply) is needed in the nonvolatile memory. This project of the paper is based on the high performance charge pump demanding of a 128k 2bit/cell NOR FLASH memory product of the Suzhou silicon heart co.ltd.This paper makes a summary about the charg pump system in the Flash memoy. It makes a detailed analysis about the charge pump operation principle and regulator operation principle. A voltage ripple formula is modified based on the traditional ripple formula. A more precise voltage ripple can be calculated by using the proposed formula. The method is that the four parrellel charge pumps are drived by four clocks from which phases there are different. A charge pump system is designed to supply the flash cell voltage during the erase operation which includes the oscillator, four phase generator, charge pump, regulator, voltage bandgap reference and power on reset circuit. The charge pump will have a large area and big voltage ripple because of the large current loading and high output voltage. So the three schemes are used to improve the performance. First a stable oscillator is proposed which can decrease the charge pump area in the slow corner. Second the four clocks of the different phases are used to drive the charge pumps which are composed of the four parallel charge pumps which decrease the ripple. Third the high PSRR regulator is used to regulating the 7v charge pump output which gets a small ripple.A 3.3v charge pump is implemented at the UMC 0.18um embedded flash process. The test chip implements the 1.8v to 3.3v voltage boost function. And the test results match the design results basicly. And the paper makes a detaild description of the 7v charge pump design. The UMC 0.18um embedded flash procees model is used to simulation. The simulation results show that the proposed charge pump systems obtain the better performance than the conventional. The chip has been taped out, but the silicon results have not come out. So the practical performance is waited for testing and verifying.