Design And Implementation Of High Energy Efficiency UHF Analog Front End

Radio frequency identification is a wireless communication technology that uses radio frequency signals to conduct non-contact communication to identify target objects.UHF RFID technology plays a key role in military,transportation,and logistics.In this thesis,with the goal of high energy efficiency,the key circuits of passive UHF RFID analog frontend are designed and implemented in the process of UMC 0.18 um EEPROM.It is in line with international protocol standards of EPC Global C1 G2.Firstly,based on the theoretical basis and working principle of the energy harvesting circuit,a master-slave charge pump structure with high rectification efficiency under low input power is designed.The boosting speed is fast and the driving ability is strong;combined with the structure and the performance parameters of the traditional voltage stabilizing circuit,a low-dropout linear regulator that is suitable for low power consumption and requires high output current is given in this work.Secondly,the demodulation circuit and modulation circuit are researched and designed;the power-on reset circuit is designed to provide the reset signal to the digital section;and the current-controlled ring oscillator with digital calibration technology is used to provide the clock signal for the digital section.Based on the UMC 0.18?m EEPROM process,the simulation and measurement results of each circuit module are given.Measurement results show that the chip's actual sensitivity is-10 dBm,the charge pump's rectification efficiency is 22.6%;the output voltage of LDO is 1.1V which fluctuation is less than ± 2%;demodulation circuit and power-on reset circuit meet the design requirements,the clock circuit generates 1.92 MHz frequency.The area of the analog front-end core is 533?m*817?m,and the power consumption is 24 uW.Based on the measurement results,the circuit is optimized and verified by simulation: the charge pump reverse leakage current problem is improved,and its energy conversion efficiency is improved;the structure of the LDO is improved,and the influence of the load change is reduced to improve its accuracy;and the control clock is passed through.The bias current circuit is improved to reduce clock instability.