Research On Testability And Low Power Design Method In VLSI High-Level Synthesis

The testability and power dissipation of circuit have become the principal problems in the design of very large scale integration (VLSI) due to the rapid development of semiconductor technique and the constant improvement of integration level and clock frequency of VLSI. Nowadays, many studies show that high-level design can maximally optimize testability and power dissipation as a result of its little dependence on implementation and high freedom of algorithm and architecture. In addition, algorithm and architecture have a remarkable effect on hardware testability and power dissipation, which can make satisfying optimal effects on testability and power dissipation of final circuit. Therefore, high-level test synthesis and high-level low power synthesis draw wide attention of academic world. This dissertation provides an up-to-date review of high-level synthesis (HLS), testability and low power design, on the basis of which a deep research is carried out on high-level test synthesis and high-level low power synthesis. Thus, the problems currently facing the development of integrated circuit can be solved through the combination of HLS, testability and low power. The major contributions of this dissertation are as follow:1) A register allocation method for testability is proposed on the basis of weighted compatibility graph. A weighted formula of compatibility graph edge based on the rules of high-level synthesis for testability is provided, and an improved weighted clique partition algorithm is used to deal with this weighted compatibility graph. Thereby, four rules for testability can be considered simultaneously in the procedure of register allocation and the goal of improving circuit testability is achieved. Experimental results show the effectiveness of this method for testability.2) A high-level low power synthesis method for control flow intensive design is proposed based on the analysis and the study of high-level power optimization of control flow intensive design. The operation procedure of this method is as follows: first schedule the control nodes in control data flow graph, then establish control edges between control nodes and the target transitive fanins, shut down unnecessary operate notes to save power dissipation, next reschedule the scheduled control data flow graph by using power dissipation optimization scheduling method based on multiple voltages to maximize optimization of circuit power dissipation. This method can not only perfectly satisfy the needs of power dissipation optimization in control flow intensive design, but also be suitable for data flow intensive design. Experimental results have shown its high power dissipation optimization quality and low algorithm time complexity.3) After the deep study of high-level test synthesis and high-level low power synthesis, a high-level testability and low power synthesis method based on genetic algorithm is proposed, which combines testability design and low power design. Under time and area constraint, this method studies the testability and low power by way of high-level scheduling and module allocating. Through weighted form, a single fitness function is obtained, which can reflect the requirements of each subobjective. Thereby, the multi-objective optimization problem can be converted to a single objective problem. Besides, a chromosome coding of genetic algorithm is proposed that can be used for high-level scheduling and module allocating simultaneously, and one point crossover operator based on data dependence and mutation operator based on control step constraint are designed, hence, avoiding the generation of infeasible solutions. The efficiency of testability improvement and power dissipation optimization of this method is demonstrated by experimental results.