Research On High Level Test Synthesis Based On PSA

As advances are made in IC process technology, the number of transistors that can be fabricated on a single IC increases. The magnitude of the design effort also grows with circuit density., the testing work become more and more important. related for such complex circuits. Therefore,we should consider test in the high level design process.Recent works have proved the necessity of considering testability as one of the design constraints during High Level Synthesis.because the high level description can be implemented with many structures,so it has enough space to optimize .high level test synthesis is widely researched in the past twenty five years .now the main research concentrated on area ,delay and power consuming.Our work are based on high level test synthesis and polynomial symbolic algebra, PSA is a mature IC computation model,in previous work,it is applied in many fields,such as Polynomial Representation of Circuit Containing Branches,high level synthesis,formal verification .we first try applied this theory in the field of high level test synthesis,represent the testability structure with symbolic algebra, to complete the high level test synthesis through the representation and computation of polynomial symbolic algebra.The main objective of this paper is propose a high level testability synthesis method based on PSA, obtain the circuit description based on PSA firstly ,Then get the testable structure representation with inserted BIST structures, After the testability analysis, propose an integrated schedule and allocation algorithm based on polynomial symbolic algebra. In this process we alse explore the technology of resource sharing based on PSA. At last we get the final netlist description. And our algorithm can reduce the test time and hardware overhead, the experiment results proved the effectivity of our method.