High-level testability analysis and optimization

Testing of VLSI circuits to catch defects is a very important part of the manufacturing process. It enables integrated circuit (IC) manufacturers to guarantee the quality of their products so that consumers may use them with confidence. The cost of testing ICs can be as high as 30% of the total manufacturing cost. This thesis provides solutions to the growing problem in the VLSI design world--the increasing cost of testing VLSI circuits with their ever growing sizes and complexity. Recently, the testing problem has been further aggravated with the advent of core-based systems-on-a-chip. A core-based system-on-a-chip is composed of a number of pre-designed, pre-characterized, and pre-verified functional blocks called cores (or Intellectual Property).; Traditional testing techniques target the problem at the later phases of the design cycle. Automatic test pattern generation techniques (ATPG) at the logic level require large amounts of computing time and resources for testing even moderately sized sequential circuits. With the pressure of time-to-market of ICs mounting on manufacturers, test solutions using just ATPG have become almost unacceptable. Hence, designers use certain design-for-testability (DFT) or test insertion techniques and modify the circuit to ease the task of test generation at the expense of test overheads. Even such DFT methods, like scan design or built-in self-test (BIST) can incur large area, performance, and power overheads, if introduced at the lower levels of the design cycle. Currently, there is also a trend towards designing at the higher levels of abstraction motivated by the growing complexities of electronic systems, shrinking product cycle times that require faster time to market, and the emergence of electronic design automation (EDA) tools that support automatic synthesis starting from architectural and algorithmic design descriptions. All the above facts point to the need of testing and DFT techniques at higher levels of the design cycle. This thesis presents a suite of techniques to automatically perform testability analysis and optimization for designs at the architectural or register-transfer level (RTL) and system level of the design hierarchy.; High-level (or behavioral) synthesis refers to the process of synthesizing, from an abstract behavioral description, an RTL implementation that satisfies the desired constraints. High-level synthesis techniques for minimizing area, maximizing performance, and enhancing testability of the synthesized design have been investigated. This thesis first presents techniques for test generation and DFT for poorly testable RTL circuits which have been obtained by behavioral synthesis, i.e., when prior behavioral information is available. However, if circuits are designed at the RTL directly, then behavioral information may not be available. This thesis next provides techniques for test generation and test insertion at the RTL even when prior behavioral information is unavailable. The thesis also presents DFT and test generation techniques for programmable data paths like application-specific programmable processors (ASPPs) and application-specific instruction processors (ASIPs). It further shows how RTL circuits may be tested with BIST using high-level testability analysis techniques. Finally, it proposes a testing and DFT technique for systems-on-a-chip built with embedded cores. Building on these insights, a high-level test generation and DFT tool has been developed that aims at reducing testing costs while enhancing testability.; The techniques and results presented in this thesis demonstrate that addressing testability issues at the higher levels of design results in significant savings in testing time and test overheads without sacrificing fault coverage.