Research On High Level Synthesis Based On PSA And Finite Field Theory

As advances are made in IC process technology, the number of transistors that can be fabricated on a single IC is increasing rapidly,the progress of manufacture technology chanllenges the traditional design methodology of ICs,all of this promotes the updating of the electronic design methods and tools in some cases.As the absolutely necessary stage in EDA design process, high level synthesis becomes people's research hotspot..High level synthesis has been widely researched in the past twenty five years. The major research for high level synthesis concentrates on satisfying the constraints of testability,area ,delay and power consuming nowadays.This thesis focuses on the high level synthesis, and the major work is as follows.Firstly, the development of IC technology pose new requirements for high level testability. the testabillity synthesis algorithm based on high level testability analysis and enhancement is given. High level testability analysis approach HLTA-PSA based on PSA model , the whole polynomial description of circuits is then constructed using critical path sensitization. The testability parameters of polynomial operation are extracted,and the testability of circuits is analysised and computed.The testability of the whole circuits is enhanced according to the result of testability analysis in the process of testability synthesis,and the description of circuits considering testabiliy is also given finally.It can reduce design time and low level test cost effectively.Secondly, with the development of EDA technology it is necessary to optimize and minimize the power dissipation in high level synthesis, therefore low power synthesis research based on PSA is conducted. A high-level low power data-flow synthesis method is firstly considered based on horner form. The function representation of circuits using horner form is then transformed to get the final polynomial form, the data-flow based on horner form then perform scheduling,allocation and binding work in high level synthesis. the effect of binding and layout in the process of synthesis is considered. A power reduction of about 40% is then got under the limit of performance and area.After that a new scheduling method considering PDP restriction in the process of high level synthesis schedule is proposed. It extracts the parameter of delay and construct the objective equation, a new optimization approach based on Genetic Algorithm (GA) is proposed. At last a synthesis framework under the multiple word length environment is given,it achieves a power reduction of 22.9% compared to ordinary optimization method based on area or delay.Thirdly, this thesis proposed high level synthesis approach based on finite field theory. First, to optimize imprecise polynomial circuits using arithmetic transformation, implement the design under different error precision bound and considering the case of fixed point and floating point representation., to search the optimized circuits with branch and bound algorithm. And then implement datapath polynomial optimization by polynomial decompostion(including univariate polynomial decomposition and Multivariate Polynomial decompostion) . The polynomial datapath circuits is constructed with the components from the library, an ILP model is applied to solve the library element mapping technqiue. This thesis also explores the expression control technique (THR reduction and variable substitution and elimination),such methods can efficiently reduce the redundancy in polynomial datapath without changing circuit performance. with the above contribution the datapath optimization based on minimum design parameters (including components,delay,power and so on) is obtained.