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Research On Low Power High Level Synthesis Algorithm In VLSI Design

Posted on:2012-02-17Degree:MasterType:Thesis
Country:ChinaCandidate:Y Z QuFull Text:PDF
GTID:2178330335452392Subject:Measuring and Testing Technology and Instruments
Abstract/Summary:PDF Full Text Request
Very Large Scale Integrated circuit (VLSI) design is very important to modern industry. Currently, the manufacture standard of semiconductor device has move into 32nm era. As the advance of circuit technology, the requirement for Electronic Design Automation (EDA) tools is increasing too. The core part of any EDA tool lies in the algorithm.High Level Synthesis (HLS) is a critical procedure following the behavior description of the circuit function. It is the first step of doing physical design of a chip. The purpose of high level synthesis is to assign function unit for each operation in the behavioral description. Also, each operation will be assigned a certain time slot for it to be executed. Generally, HLS algorithm take a system behavior description as input and output a Register Transfer Level (RTL) circuit, which will be transfer into a real circuit after placement and routing, etc.Presently, industry development tools only consider the case that there is only one function unit--each function has its own layout, delay, area, etc. Based on this scenario, they will do scheduling, allocating and binding. Notice that each operation could be performed on different function unit corresponding to different circuit in transistor level; we propose using multiple function units for each operation to do high level synthesis. By doing that it brings us the benefit of further optimizing the total resource, and therefore optimizing power and area.One thing to keep in mind is that high level synthesis problem is NP-Complete, that means it is impossible to find the optimal solution in limited time. As we choose to use multiple function units, the solution space will be even larger, and increase the problem complexity to some extent. However, it also gives us much more opportunity to get a better solution. In this paper, an improved Simulated Annealing algorithm is proposed to solve the problem.We compared our algorithm with existing algorithm. Our algorithm gets much better results in the most cases, and the average savings of power is 17.7%, while the running time is within the reasonable range.
Keywords/Search Tags:VLSI, High Level Synthesis, Scheduling, Simulated Annealing, Force Directed Scheduling
PDF Full Text Request
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