Research On Low Power Techniques Of High Level Synthesis Design In VLSI

With today's increasingly large and complex digital integrated circuit (IC) and system-on-chip designs, power dissipation has emerged as a primary design consideration. Reduction of power consumption in VLSI designs can be achieved at various levels of the design hierarchy, ranging from processing technology, circuit, logic, architectural and algorithmic (behavioral) levels, up to system level. It has also been long recognized that the most dramatic power saving is achievable at the algorithm and architecture levels, where computations are normally described using data/control flow graphs. Thus, in this thesis, a multiple supply voltage IC is synthesized at the high level.In this thesis, a tabu-search-based behavior level synthesis scheme is proposed to minimize power consumption with resources operating at multiple voltages under the timing and the resource constraints. Unlike the conventional methods where only scheduling is considered, our synthesis scheme considers both scheduling and partitioning simultaneously to reduce power consumption due to the functional units as well as the interconnects among them. In particular, we have configured our solutions as a three-tuple vector to account for both the schedule and the partition. Cycling of the same solutions is prevented by applying a tabu list with an update mechanism enhanced with an aspiration function. In this way, the algorithm can search a large solution space with fast convergence rate. Experiments with a number of DSP benchmarks show that the proposed algorithms achieve an average power reduction by 49.6%.In this thesis, a Simulated-Annealing-based behavior level synthesis scheme is proposed to minimize power consumption with resources operating at multiple voltages under the timing and the resource constraints. Our synthesis scheme considers both scheduling and partitioning simultaneously to reduce power consumption due to the functional units as well as the interconnects among them. In particular, we have configured our solutions as a three-tuple vector and have got it by many iterations under the controlled temperature. The advantage of this algorithm is that it can avoid local optimization and converge whole optimization. Experiments with a number of DSP benchmarks show that the proposed algorithm is effective for low power design.In this thesis, a scheduling scheme based on dynamic frequency clocking and multiple voltages is proposed for low power designs under the timing and the resource constraints. Unlike the conventional methods at high level synthesis where only voltages of nodes were considered, the scheme based on a gain function considers both voltage and frequency simultaneously to reduce energy consumption. Experiments with a number of DSP benchmarks show that the proposed scheme achieves an effective energy reduction.A high level synthesis scheme based on multiple voltages is proposed for low power design in VLSI. This scheme considers both scheduling and interconnection to reduce power. In GAIN scheduling, the priority function includes the power gain, the mobility, and the computation density of an operation. The transition activities on the signal lines and the coupling capacitances of the lines are considered simultaneously in interconnection. This scheme is realized in CDFG Toolkits and its efficiency is proved.From System-on-chip to Network-on-chip, the main dissimilarity is replacing the bus with the network. How connect, how formative network function is related to topology structure. In this paper we propose a topology structure for NoC, and compare it with other topology networks by five kinds of mainly properties : node degree, network diameter, connectivity, the average most short-circuit path and the average shortest wire length. Experiment results show that this topology has better performance on cost/performance layout.CDFG Toolkits provide a set of software tools convenient and practical for high level synthesis. The CDFG toolkit includes CDFG generator, CDFG to C (VHDL) converter, CDFG parser, and CDFG viewer. The CDFG Toolkits have been proved by our research work.