Research On SoC Test Resources Optimization

SoC test has attracted researchers' attention for years.However with theincreasing complexity and scale of IC in VDSM(Very Deep Submicron),IC testgrows costly and time-consuming,as poses severe challenges to SoC test.Moreover test resources such as storage capacities of external equipment and thenumber of test channels don't satisfy the test requirements.Consequently SoC testresources optimization is necessary for cost-effective test.This thesis exploresSoC test data compression,SoC test scheduling and low power SoC test from theperspective of reducing test channels requirement,ATE storage requirement,testapplication time and power dissipation.The contributions of the thesis conclude:Firstly,this thesis presents a novel approach to core-based SoC testcompression.At first setp,the test vectors from different test sets are overlappedto the maximum limit to form overlapped test vectors,then Variable-Run-Length(VRL) coding is applied to the overlapped test vectors.Hence the two-levelcompressed test data are formed.Due to the fact that the test application time is inproportional to the length of overlapped test vector,and the length of actualoverlapped vectors is far less than that of the sum of the length of test vectors,thetest application time is reduced significantly.And VRL handles both run length ofzero and run length of one,thus maximizing the coding efficiency.Experimentalresults show that the proposed method achieves the highest test compression ratioof 67.4% and the lowest 39.5%,while the average test compression ratio reaches56%.In the best case,test data is reduced by 12.3 times.In addition to a few cases,the proposed method consumes the least test time.Secondly,this thesis presents a method for SoC test compression and testscheduling based on test response reuse idea.The test sets are preprocessed beforetest.The test responses from previous cores are used to compress the test stimuliof current cores under test through preprocessing.Then delete the test vectorsfrom the test set of current cores under test,when such test vectors are compatible with the test responses of previous cores.During the actual test procedure,for allthe cores except the last one,if their corresponding test vectors are compatiblewith the test stimuli of next cores,then take the test responses of current coresunder test as the test inputs of next cores.Then repeat the above operations untiltest vectors of all the cores are processed.If the test responses of previous core arenot compatible with the test vectors to be applied,then fetch the test data ofcurrent cores under test directly from ATE.On hardware implementation,only acouple of 2-to-1 MUXs are needed to control where the test data come from.Theadjustment heuristics for test sequences of cores under test,and those of testvectors application corresponding to each cores under test are outlined to get theoptimal test effect.The proposed method does not require decoder,thus requireslittle hardware overhead.Power constrained core test pipelining further reducestest application time.For test response reuse-based SoC test scheduling,hierarchical clustering STS-HC is adopted for test time minimization.Comparedto previous published methods,this method is easy to implement and consumeslittle hardware.Experimental results on benchmarks show that,compared to theexisting methods,STS-HC consumes the least test time and that our testcompression ratio is relatively higher.The average test compression ratio reachesup to 50%.In addition,the fault coverage for SoC benchmark circuit p93791 andp34932 is increased by 1.32% and 5.08% respectively.Therefore algorithmSTC-TR increases fault coverage of some test sets,at least it does not compromisethe fault coverage of each test set.Thirdly,this thesis presents process algebra-based SoC test scheduling.Testpipelining can be adoPted to minimize test application time.However,in order toavoid the high test power destroying system under test,the test power occurredduring test is to be kept under control.Process algebra is known for handlingconcurrent processes.This thesis forms time-labeled-transition-system model forconcurrent processes based on process algebra,and establishes some theoremsand definitions to convert the former to the ACSR(Algebra of CommunicatingShared Resources) description.And SoC test scheduling model STS-ACSR is outlined.The concurrent SoC test is mapped into concurrently executed processes,and test resources are modeled as ACSR resources.Priority assignments avoid testconflicts.Thus the power constrained SoC test achieves maximum testconcurrency and least test application time.The experimental results prove theefficiency of process algebra in handling SoC test scheduling in comparison to theclassical algorithms.