The Design And Implement Of Instruction Decode&Control Unit In FT-C55LP

Digital signal processor (DSP) is a processor of high performance, which specializes in real-time processing of large-scale digital signals. DSP is widely applied to the fields of automobile, communication, home appliances, Medicare, industrial control, aviation and so on. This subject comes from a fixed-point DSP project ----FT-C55LP, which is characterized by high performance and low power-consumption. I am very lucky to have an opportunity to participate in the DSP research and undertake the task of designing the controlling parts for instruction decoding, which then generates my article here.Based on the in-depth research of FT-C55LP's characteristics of instruction sets and instruction parallel, I have a comprehensive and detailed analysis of the instruction sets of FT-C55LP, and put forward a design plan of decoding controlling unit, which is divided into three modules: parallel instruction splitting, single instruction decoding, and decoded signal incorporating.The instruction decoding and controlling unit can receive 4 bytes program codes and store them into the instruction buffer queue (IBQ) in which one 1-7 bytes single instruction or parallel instruction is transmitted。In Pre-decode stage,The instruction decoding and controlling unit can identify where instructions begin and end, and the length of the instruction, as well as identify instruction parallel and addressing mode expansion, then send these Pre-decode information and 1-6 bits instruction codes to the encoder. The instruction decode has 3 functional modules.1. Parallel instruction splitting module. This module splits a parallel instruction into two single instructions and sends them to the following decoding modules respectively.2. Single instruction decoding module. This module has a realization of the single instruction decoding. Based on the DSP's instruction features such as code compression and variable length, I adopt centralized decoding and optimize the interface of the other 3 functional units.3. Decoded signal incorporating module. This module incorporates the controlling signals coming from the decoded module, then dispatching the incorporated signals and data to the other 3 functional units.And then, I formulate a detailed verification program for the instruction decoding and controlling unit. By using the ModelSim simulating tool, I perform a simulating function on the instruction decoding and controlling unit, and obtain a correct simulating result. Through the Code Coverage tool, I analyze the code coverage of this unit, and find that the effect is satisfying. Finally, by the means of Design Compiler tool I synthesize logically the RTL code of the instruction decoding and control unit, and the synthesis results meet the design requirements.