Design Of Configurable And Extensible Media Processor

Video applications are computationally intensive, stretching the capabilities of current embedded processors. In this dissertation, the architecture design and VLSI implementation of a configurable and extensible media processor is presented, which support multi-standard video applications. In the design, an embedded RISC core and an EDO-SIMD video processing engine were integrated with the DMA etc. via AMBA bus and dedicated communication channel as a high performance and low power heterogeneous multi-core platform. The research has made valuable exploration on following three aspects:First, configurable extensible embedded RISC processor design, especially cache and memory management unit (MMU) in memory subsystem.A RISC processor CK520 is designed based on 32-bit CK-CORE instruction set architecture. A way combined based on-line configurable cache and 2-level TLB MMU micro-architecture is proposed in memory subsystem design. Micro-architecture and memory subsystem of CK520 is parameristic, some parameters such as instruction cache and data cache size, way associativity, replace scheme, the size of MMU TLB, branch prediction etc are configurable. The application specific instruction such as MAC can be implemented via extending data path of basic core, while the programmable accelerator can be attached through coprocessor interface. So the CK520 can provide traditional programmability, as well as adaptability and efficiency via configuration and extension.Second, EDO-SIMD (embedded data organization SIMD) instruction set architecture and video processing engine design for multi-standard video processing acceleration. The features of video application and algorithm were summarized, through analysis on the typical video application benchmarking results. It was found that the operands involved some matrix, sequential, butterfly, broadcast and delay line skew addressing mode. In traditional SIMD media instruction set architecture, these operands organization overhead is obstacle to improve the performance and hardware efficiency. So a SIMD instruction set architecture with embedded data organization (EDO-SIMD) is proposed.EDO-SIMD is not designed as extension to RISC CPU, but designed as a standalone processor architecture optimized for video processing. The features of EDO-SIMD ISA is programmability and flexibility to support multi-standard video codec, embedded data organization instruction and video application specific instructions to boost video processing performance, simplicity for low cost and low power constrained embedded system, scalability and configurability to adapt with application requirements.In the micro-architecture design of video processing engine, a parametric and modular design methodology is applied to support configurable vector length, and a 32-bit data path is desgined as 1-way, and full data path can be tiled to LMAX/4 way according to application performance requirements. Vector permutation networks are inserted into operands reading ports and result store path to support embedded data organization instructions. In ALU and multiplier design, gated bits and split module scheme are use to support various data precision operations including byte, half word and word . And the on chip data memory is byte addressable double data buffer structure, so that the unaligned data load and store can be supported and data can be prepared by DMA engine concurrently with computing.Finally, a video application specific SoC platform design and optimize. In video SoC platform, the embedded RISC processor and EDO-SIMD video processing engine were integrated with the DMA and LCDC etc. IP based on AMBA SoC interconnection and dedicated communication channel. The platform can exploit data level parallelism, instruction level parallelism and task level parallelism. The RISC processor can schedule the tasks on video engine and configure and kick off DMA transaction efficiently in a remote procedure call mode. The platform can be configured and extended to fulfill the application requirements, and get a high performance low power video system solution.The research methodology that application, algorithm, architecture, VLSI implementation are considered seamless, as well as the configurable, extensible, parametric and modular design methodology, are valuable for the embedded processor and SoC design.