Key Circuits And EDA Techniques Research Of High Performance DSPs

Digital signal processors (DSPs), a class of embedded microprocessors optimized for digital signal processing, have become a key component in many multimedia appliances, communication devices, medical instruments, and industrial products. Improving circuit designs, such as employing advanced circuits and new circuit design methodology, are vital to enhance the performance of DSPs. EDA techniques play an important role in design methodology. The circuit design techniques of high performance DSPs are researched in this thesis, with an emphasis on key circuits and EDA techniques. The main contributions are as follows:1. To reduce the power of dynamic circuits, limited dynamic circuit design methodology has been proposed. Combining with the design of a 32-bit adder loop, the key techniques of this methodology are introduced, such as selection and design of dynamic circuits, clock design, delayed precharge, dual-mode circuits, and noise control method. Simulation results showed that dynamic power has been reduced by 52.78% when compared to fully dynamic circuits.2. Port multiplex techniques has been proposed in the design of a register file with 13 read ports and 9 write ports. The number of decoders and the ports of register cells have been both reduced by seven. Channel-enhanced Dual-Vt bitline has been proposed to improve the noise stability and to reduce leakage power of the dynamic read bitlines. For 90nm CMOS process, the proposed bitline has great advantage over the pseudostatic bitline. Compared to LBSF bitline, dynamic power is reduced by 28.5% and the leakage power is reduced by 2-3 orders with an area overhead of 9.5%.3. An algorithm of a 16-bit hybrid multiplier has been proposed. The proposed algorithm is based on the radix-4 modified Booth's algorithm. The algorithm generates ten partial products and one modifier, which is six less than the other algorithms. The delay, power and area are all reduced by more than 20%. The multiplier has been designed in 180nm CMOS process by full custom design and a test chip has been fabricated. The test results showed the multiplier works well at 404.8MHz in normal mode, and 475.2MHz in SIMD mode.4. Key algorithms for functional model extraction of transistor-level circuits have been proposed. A transistor-level functional model extractor named TranSpirit has been coded in C/C++. The experimental results showed TranSpirit has high speed and can meet the functional verification requirements of unit-level full custom designs. 5. Key techniques of transistor-level hybrid timing analysis methods have been studied. Test waveform generation algorithms for max and min delay considering multiple inputs simultaneous switching have been proposed. A transistor-level hybrid timing analysis tool named SpiceTime is coded in C/C++. The errors of max and min delay of SpiceTime are less than 2.89% and 7% respectively when compared to Hspice. Experimental results showed that SpiceTime has higher efficiency than Hspice. The effect of multiple inputs simultaneous switching on path delay has also been studied.6. Timing verification of limited dynamic circuits has been studied. Based on the four-event periodic waveform models, the timing constraints for HI-CMOS, LO-CMOS, NTP dynamic circuits and N-C~2MOS have been constructed. Hybrid timing analysis method has been applied to calculate the delay of dynamic circuits for the first time. Delay test waveform generation algorithms for dynamic circuits have been proposed. The algorithms have been implemented in SpiceTime and applied to the design of a 32-bit adder based on limited dynamic circuits. It helped to increase the design efficiency and find several design problems. Without false paths, the errors of evaluation delay and precharge delay are within 3.62% and 8.26% respectively.The research in this dissertation provides a practical solution for implementing the datapath of YHFT-DSP/MHM. The research lays a solid foundation for further investigation on high performance DSP designs.